© 2007 Fairchild Semiconductor Corporation

www.fairchildsemi.com

SG6859A Rev. 1.0.0

8

Operation Description

SG6859A devices integrate many useful designs into

one controller for low-power, switch-mode power

supplies. The following descriptions highlight some of

the features of the SG6859A series.

Start-up Current

The start-up current is only 9μA. Low start-up current

allows a start-up resistor with high resistance and low-

wattage to supply the start-up power for the controller. A

hold-up capacitor are sufficient for an AC-to-DC power

Operating Current

The operating current has been reduced to 3mA. The

low operating current results in higher efficiency and

reduces the VDD hold-up capacitance requirement.

Green-Mode Operation

The proprietary green-mode function provides off-time

modulation to linearly decrease the switching frequency

under light-load conditions. On-time is limited to provide

stronger protection against brownouts and other

abnormal conditions. The feedback current, which is

sampled from the voltage feedback loop, is taken as the

reference. Once the feedback current exceeds the

threshold current, the switching frequency starts to

decrease. This green-mode function dramatically

reduces power consumption under light-load and zero-

load conditions. Power supplies using the SG6859A

can meet even the strictest regulations regarding

standby power consumption.

Oscillator Operation

A resistor connected from the RI pin to ground

generates a constant current source used to charge an

internal capacitor. The charge time determines the

internal clock speed and the switching frequency.

Increasing the resistance reduces the amplitude of the

and the switching frequency is:

(kHz)

)

(k

R

6650

f

I

PWM

Ω

=

(1)

Leading-Edge Blanking

Each time the power MOSFET is switched on, a turn-on

spike occurs at the sense-resistor. To avoid premature

termination of the switching pulse, a 320ns leading-

edge blanking time is built in. Conventional RC filtering

can be omitted. During this blanking period, the current-

limit comparator is disabled and cannot switch off the

gate driver.

Constant Output Power Limit

When the SENSE voltage across the sense resistor,

output GATE drive is turned off following a short

propagation

delay,

This

propagation

delay

introduces

an

additional

current

proportional

to

voltages result in larger additional currents. At high

input line voltages, the output power limit is higher than

at low input line voltages. To compensate for this output

power limit variation across a wide AC input range, the

threshold voltage is adjusted by adding a positive ramp.

This ramp signal rises from 0.8V to 1V, then flattens out

at 1V. A smaller threshold voltage forces the output

GATE drive to terminate earlier, which reduces the total

PWM turn-on time and makes the output power equal to

that of low line input. This proprietary internal

compensation ensures a constant output power limit for

Under-Voltage Lockout (UVLO)

The turn-on and turn-off thresholds are fixed internally

at 16.5V and 9.5V. During start-up, the hold-up

capacitor must be charged to 16.5V through the start-up

resistor to enable the SG6859A. The hold-up capacitor

continues to supply VDD until power can be delivered

must not drop below 9.5V during this start-up process.

This UVLO hysteresis window ensures that hold-up

Gate Output

The BiCMOS output stage is a fast totem pole gate

driver. Cross conduction has been avoided to minimize

heat dissipation, increase efficiency, and enhance

reliability. The output driver is clamped by an internal

17V Zener diode to protect power MOSFET transistors

against undesired over-voltage gate signals.

Built-in Slope Compensation

The sensed voltage across the current-sense resistor is

used for current-mode control and pulse-by-pulse

current limiting. Built-in slope compensation improves

stability and prevents sub-harmonic oscillations due to

peak-current mode control. The SG6859A has a

synchronized, positively-sloped ramp built-in at each

switching cycle. The slope of the ramp is:

Duty(max.)

Duty

0.36

×

(2)

Noise Immunity

Noise from the current sense or the control signal can

cause significant pulse-width jitter, particularly in

continuous-conduction mode (CCM). While slope

compensation helps alleviate these problems, further

precautions should still be taken. Good placement and

layout practices should be followed. Avoiding long PCB

traces and component leads, locating compensation

and filter components near the SG6859A, and increasing

power MOS gate resistance improve performance.