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STPC4HEBI Datasheet(PDF) 40 Page - STMicroelectronics

Part No. STPC4HEBI
Description  X86 Core PC Compatible Information Appliance System-on-Chip
Download  93 Pages
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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STPC4HEBI Datasheet(HTML) 40 Page - STMicroelectronics

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ELECTRICAL SPECIFICATIONS
40/93
Release 1.5 - January 29, 2002
4.5.3. SDRAM INTERFACE
Figure 4-5, Table 4-10 lists the AC characteristics
of the SDRAM interface.
For correct operation, the programmable read
clock delay (RDCLK) must be activated for the
CRTC and the delay set to the minimum. This is
done by setting the Latch_CRTC_Data_In bit in
the SDRAM Controller register 0 and clear the
bits[3:0] in register 1.
The PC133 memory is recommended to reach
100MHz operation.
Figure 4-5. SDRAM Timing Diagram
MCLKI
STPC.output
STPC.input
MCLKx
Tdelay
Tsetup
Thold
Toutput (min)
Toutput (max)
Tcycle
Thigh
Tlow
Table 4-10. SDRAM Bus AC Timing
Name
Parameter
Min
Typ
Max
Unit
Tcycle
MCLKI Cycle Time
10
ns
Thigh
MCLKI High Time
4
ns
Tlow
MCLKI Low Time
4
ns
MCLKI Rising Time
1
ns
MCLKI Falling Time
1
ns
Tdelay
MCLKx to MCLKI delay
-0.9
ns
Toutput
MCLKI to Outputs Valid
5.2
7
ns
MCLKI to DQM[ ] Outputs Valid
6.5
8.8
ns
MCLKI to MD[ ] Outputs Valid
6.5
8.8
ns
Tsetup
MD[63:0] setup to MCKLI
3.75
4.0
ns
Thold
MD[63:0] hold from MCKLI
1.3
2.5
ns
Note: These timing are for a load of 50pF.


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