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STPC4HEBI Datasheet(PDF) 30 Page - STMicroelectronics |
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STPC4HEBI Datasheet(HTML) 30 Page - STMicroelectronics |
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30 / 93 page 
STRAP OPTIONS 30/93 Release 1.5 - January 29, 2002 3.1.3. ADPC STRAP REGISTER 2 CONFIGURATION Strap2 Access = 0022h/0023h Regoffset = 04Ch 76543210 See Table below Rsv MD[20] MD[19] MD[18] See Table below Rsv This register defaults to the values sampled on MD pins after reset Bit Number Sampled Mnemonic Description Bits 7 Rsv For the parts referenced STPCC4, Reserved MD[40] For the parts referenced STPCC5, this bit reflects the value sampled on MD[40] is used is used to set the clock multiplication factor of the 486 core, as follows: MD[40] 0 DX (X1) 1 DX2 (X2) This strap is not readable in a register for the STPCC4. Bit 6-5 Rsv Reserved Bits 4 MD[20] This bit reflects the value sampled on MD[20] pin and controls the Dot clock (DCLK) source as follows: 0: External. DCLK pin is an input. 1: Internal. DCLK pin is an output and is connected to the internal frequency synthesizer output. Note this bit is writeable as well as readable. Bit 3 Rsv Reserved Bit 2 Rsv Reserved Bit 1 MD[17] For the parts referenced STPCC4, see section Section 3.1.1.bits 1:0. Rsv For the parts referenced STPCC5.This bit is reserved and not connected Bit 0 Rsv Reserved |
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