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STPC4HEBI Datasheet(PDF) 28 Page - STMicroelectronics |
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STPC4HEBI Datasheet(HTML) 28 Page - STMicroelectronics |
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28 / 93 page 
STRAP OPTIONS 28/93 Release 1.5 - January 29, 2002 3.1. POWER-ON STRAP REGISTER DESCRIPTIONS 3.1.1. ADPC STRAP REGISTER 0 CONFIGURATION Strap0 Access = 0022h/0023h Regoffset = 04Ah 76543210 MD[7] MD[6] See Table below MD[4] Rsv See Table below See Table below See Table belowl This register defaults to the values sampled on MD[7:4] pins after reset Bit Number Sampled Mnemonic Description Bits 7-6 MD[7:6] PCICLK PLL set-up: The value sampled on MD[7:6] controls the PCICLK PLL programming according to PCICLK frequency. MD7 MD6 0 0 PCICLK frequency between 16 & 32 MHz 0 1 PCICLK frequency between 32 & 64 MHz 1 X Reserved Bit 5 MD[5] For the parts referenced STPCC4, see section Section 3.1.1.bit 2. MD[44] For the parts referenced STPCC5, this s trap selects betwen Local Bus or ISA mode. 0 = ISA Mode 1 = Local Bus Mode This strap is not readable in a register for the STPCC4. Bit 4 MD[4] PCICLK division: This bit reflects the value sampled on [MD4] and is used together with MD[17] to select the PCICLK frequency. MD4 MD17 0 X PCI Clock output = HCLK / 4 1 0 PCI Clock output = HCLK / 3 1 1 PCI Clock output = HCLK / 2 Bits 2 Rsv For the parts referenced STPCC4 These bits are reserved MD[5] Host Memory synchronization. This bit reflects the value sampled on MD[5] and controls the MCLK/HCLK synchronization. 0: MCLK and HCLK not synchronized 1: MCLK and HCLK synchronized for improved system performance. Bit 1-0 Rsv For the parts referenced STPCC4 These bits are reserved MD[4,17] For the parts referenced STPCC5. These bits reflect the values sampled on MD[17] pin and controls the PCI clock output in conjunction with MD[4], as follows: MD4 MD17 0 X PCI Clock output = HCLK / 4 1 0 PCI Clock output = HCLK / 3 1 1 PCI Clock output = HCLK / 2 |
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