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STPC4HEBI Datasheet(PDF) 22 Page - STMicroelectronics

Part No. STPC4HEBI
Description  X86 Core PC Compatible Information Appliance System-on-Chip
Download  93 Pages
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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STPC4HEBI Datasheet(HTML) 22 Page - STMicroelectronics

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PIN DESCRIPTION
22/93
Release 1.5 - January 29, 2002
..
Table 2-4. ISA / IDE Dynamic Multiplexing
ISA BUS
(ISAOE# = 0)
IDE
(ISAOE# = 1)
RMRTCCS#
DD[15]
KBCS#
DD[14]
RTCRW#
DD[13]
RTCDS#
DD[12]
SA[19:8]
DD[11:0]
LA[23]
SCS3#
LA[22]
SCS1#
SA[21]
PCS3#
SA[20]
PCS1#
LA[19:17]
DA[2:0]
IOCHRDY
DIORDY
Table 2-5. ISA / Local Bus Pin Sharing
ISA / IPC
LOCAL BUS
SD[15:0]
PD[15:0]
DREQ_MUX[1:0]
PA[21:20]
SMEMR#
PA[19]
MEMW#
PA[18]
BHE#
PA[17]
AEN
PA[16]
ALE
PA[15]
MEMR#
PA[14]
IOR#
PA[13]
IOW#
PA[12]
REF#
PA[11]
IOCHCK#
PA[10]
GPIOCS#
PA[9]
ZWS#
PA[8]
SA[7:4]
PA[7:4]
TC, DACK_ENC[2:0]
PA[3:0]
SA[3]
PRDY
ISAOE#,SA[2:0]
IOCS#[3:0]
DEV_CLK, RTCAS
FCS#[1:0]
IOCS16#, MASTER#
PRD#[1:0]
SMEMW#, MCS16#
PWR#[1:0]
Table 2-6. Signal value on Reset
Signal Name
SYSRSTI# active
SYSRSTI# inactive
SYSRSTO# active
release of SYSRSTO#
BASIC CLOCKS AND RESETS
XTALO
14MHz
ISA_CLK
Low
7MHz
ISA_CLK2X
14MHz
OSC14M
14MHz
DEV_CLK
24MHz
HCLK
Oscillating at the speed defined by the strap options.
PCI_CLKO
HCLK divided by 2 or 3, depending on the strap options.
DCLK
17MHz
MEMORY CONTROLLER
MCLKO
66MHz if asynchonous mode, HCLK speed if synchronized mode.
CS#[3:1]
High
CS#[0]
High
SDRAM init sequence:
Write Cycles
MA[10:0], BA[0]
0x00
RAS#[1:0], CAS#[1:0]
High
MWE#, DQM[7:0]
High
MD[63:0]
Input
PCI INTERFACE
AD[31:0]
0x0000
First prefetch cycles
when not in Local Bus mode.
CBE[3:0], PAR
Low
FRAME#, TRDY#, IRDY#
Input
STOP#, DEVSEL#
Input
PERR#, SERR#
Input


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