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STPC4HEBI Datasheet(PDF) 80 Page - STMicroelectronics

Part No. STPC4HEBI
Description  X86 Core PC Compatible Information Appliance System-on-Chip
Download  93 Pages
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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STPC4HEBI Datasheet(HTML) 80 Page - STMicroelectronics

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DESIGN GUIDELINES
80/93
Release 1.5 - January 29, 2002
The DIMM sockets should be populated starting
with the furthest DIMM from the STPC device first
(DIMM1). There are two types of DIMM devices;
single-row and dual-row. The dual-row devices
require two chip select signals to select between
the two rows. A STPC device with 4 chip select
control lines could control either 4 single-row
DIMMs or 2 dual-row DIMMs. When only 2 chip
select control lines are activated, only two single-
row DIMMs or one dual-row DIMM can be
controlled.
When using DIMM modules, schematics have to
be done carefully in order to avoid data buses
completely crossing on the board. This has to be
checked at the library level. In order to achieve the
layout shown in Figure 6-21, schematics have to
implement the crossing described in Figure 6-22.
The DQM signals must be exchanged using the
same order.
6.4.3.4. Summary
For unbuffered DIMMs the address/control signals
will be the most critical for timing. The simulations
show that for these signals the best way to drive
them is to use a parallel termination. For
applications where speed is not so critical series
termination can be used as this will save power.
Using a low impedance such as 50
Ω for these
critical traces is recommended as it both reduces
the delay and the overshoot.
The other memory interface signals will typically
be not as critical as the address/control signals.
Using lower impedance traces is also beneficial
for the other signals but if their timing is not as
critical as the address/control signals they could
use the default value. Using a lower impedance
implies using wider traces which may have an
impact on the routing of the board.
The layout of this interface can be validated by an
electrical
simulation
using
the
IBIS
model
available on the STPC web site.
Figure 6-21. Optimum Data Bus Layout for DIMM
Figure 6-22. Schematics for Optimum Data Bus Layout for DIMM
DIMM
STPC
SDRAM I/F
D[15:00]
D[31:16]
D[47:32]
D[63:48]
MD[31:00]
MD[63:32]
MD[15:00],DQM[1:0]
MD[31:16],DQM[3:2]
MD[47:32],DQM[5:4]
MD[63:48],DQM[7:6]
D[15:00],DQM[1:0]
D[31:16],DQM[3:2]
D[47:32],DQM[5:4]
D[63:48],DQM[7:6]
DIMM
STPC


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