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STPC4HEBI Datasheet(PDF) 7 Page - STMicroelectronics

Part No. STPC4HEBI
Description  X86 Core PC Compatible Information Appliance System-on-Chip
Download  93 Pages
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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STPC4HEBI Datasheet(HTML) 7 Page - STMicroelectronics

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GENERAL DESCRIPTION
Release 1.5 - January 29, 2002
7/93
- Peripheral activity detection.
- Peripheral timer for detecting lack of peripheral
activity
- SUSP# modulation to adjust the system
performance in various power down states of the
system including full power on state.
- Power control outputs to disable power from
different planes of the board.
Lack of system activity for progressively longer
period of times is detected by the three power
down timers. These timers can generate SMI
interrupts to CPU so that the SMM software can
put the system in decreasing states of power
consumption. Alternatively, system activity in a
power down state can generate SMI interrupt to
allow the software to bring the system back up to
full power on state. The chip-set supports up to
three power down states: Doze state, Stand-by
state and Suspend mode. These correspond to
decreasing levels of power savings.
Power down puts the STPC Consumer-II into
suspend
mode.
The
processor
completes
execution of the current instruction, any pending
decoded instructions and associated bus cycles.
During the suspend mode, internal clocks are
stopped.
Removing power down, the processor
resumes instruction fetching and begins execution
in the instruction stream at the point it had
stopped. Because of the static nature of the core,
no internal data is lost.
1.7. JTAG
JTAG stands for Joint Test Action Group and is the
popular name for IEEE Std. 1149.1, Standard Test
Access Port and Boundary-Scan Architec-ture.
This built-in circuitry is used to assist in the test,
maintenance and support of functional circuit
blocks. The circuitry includes a standard interface
through which instructions and test data are
communicated. A set of test features is defined,
including a boundary-scan register so that a
component is able to respond to a minimum set of
test instructions.


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