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STPC4HEBI Datasheet(PDF) 69 Page - STMicroelectronics |
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STPC4HEBI Datasheet(HTML) 69 Page - STMicroelectronics |
69 / 93 page ![]() DESIGN GUIDELINES Release 1.5 - January 29, 2002 69/93 In the case of higher clock load it is recommended to use a zero-delay clock buffer as described in Figure 6-8. This approach is also recommended when implementing the delay on PCICLKI according to the PCI section of the Electrical Specifications chapter. Figure 6-8. PCI clock routing with zero-delay clock buffer PCICLKI PCICLKO Device A Device B Device C PLL Device D PCICLKI PCICLKO Device A Device B Device C PLL Device D CY2305 CY2305 Implementation 1 Implementation 2 |