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STPC4EEBI Datasheet(PDF) 20 Page - STMicroelectronics |
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STPC4EEBI Datasheet(HTML) 20 Page - STMicroelectronics |
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20 / 93 page  PIN DESCRIPTION 20/93 Release 1.5 - January 29, 2002 2.2.7. VGA CONTROLLER RED, GREEN, BLUE RGB Video Outputs. These are the three analog colour outputs from the RAMDACs. These signals are sensitive to interference, therefore they need to be properly shielded. VSYNC Vertical Synchronisation Pulse. This is the vertical synchronization signal from the VGA controller. HSYNC Horizontal Synchronisation Pulse. This is the horizontal synchronization signal from the VGA controller. VREF_DAC DAC Voltage reference. An external voltage reference is connected to this pin to bias the DAC. RSET Resistor Current Set. This reference current input to the RAMDAC is used to set the full-scale output of the RAMDAC. COMP Compensation. This is the RAMDAC compensation pin. Normally, an external capacitor (typically 10nF) is connected between this pin and VDD to damp oscillations. 2.2.8. VIDEO INPUT PORT VCLK Pixel Clock Input.This signal is used to synchronise data being transferred from an external video device to either the frame buffer, or alternatively out the TV output in bypass mode. This pin can be sourced from STPC if no external VCLK is detected, or can be input from an external video clock source. VIN[7:0] YUV Video Data Input CCIR 601 or 656. Time multiplexed 4:2:2 luminance and chrominance data as defined in ITU-R Rec601-2 and Rec656 (except for TTL input levels). This bus typically carries a stream of Cb,Y,Cr,Y digital video at VCLK frequency, clocked on the rising edge (by default) of VCLK. 2.2.9. ANALOG TV OUTPUT PORT RED_TV / C_TV Analog video outputs synchronized with CVBS. This output is current- driven and must be connected to analog ground over a load resistor (RLOAD). Following the load resistor, a simple analog low pass filter is recommended. In S-VHS mode, this is the Chrominance Output. GREEN_TV / Y_TV Analog video outputs synchronized with CVBS. This output is current- driven and must be connected to analog ground over a load resistor (RLOAD). Following the load resistor, a simple analog low pass filter is recommended. In S-VHS mode, this is the Luminance Output. BLUE_TV / CVBS Analog video outputs synchronized with CVBS. This output is current- driven and must be connected to analog ground over a load resistor (RLOAD). Following the load resistor, a simple analog low pass filter is recommended. In S-VHS mode, this is a second composite output. CVBS Analog video composite output (luminance/ chrominance). CVBS is current-driven and must be connected to analog ground over a load resistor (RLOAD). Following the load resistor, a simple analog low pass filter is recommended. IREF1_TV Ref. current for CVBS 10-bit DAC. IREF2_TV Reference current for RGB 10-bit DAC. VREF1_TV Ref. voltage for CVBS 10-bit DAC. Connect to analog ground. VREF2_TV Reference voltage for RGB 10-bit DAC. Connect to analog ground. VSSA_TV Analog VSS for DACs. VDDA_TV Analog VDD for DACs. JTAG Signals VCS Line synchronisation Output. This pin is an input in ODDEV+HSYNC or VSYNC + HSYNC or VSYNC slave modes and an output in all other modes (master/slave) ODD_EVEN Frame Synchronisation Output. This pin supports the Frame synchronisation signal. It is an input in slave modes, except when sync is extracted from YCrCbdata, and an output in master mode and when sync is extracted from YCrCb data The signal is synchronous to rising edge of DCLK. The default polarity for this pin is: - odd (not-top) field: LOW level - even (bottom) field: HIGH level 2.2.10. MISCELLANEOUS SPKRD Speaker Drive. This the output to the speaker. It is an AND of the counter 2 output with bit 1 of Port 61, and drives an external speaker driver. This output should be connected to 7407 type high voltage driver. SCL, SDA I²C Interface. These bidirectional pins are connected to CRTC register 3Fh to implement DDC capabilities. They conform to I2C electrical specifications, they have open-collector output drivers which are internally connected to VDD through pull-up resistors. |
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