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STPC4EDBI Datasheet(PDF) 43 Page - STMicroelectronics

Part No. STPC4EDBI
Description  X86 Core PC Compatible Information Appliance System-on-Chip
Download  93 Pages
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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STPC4EDBI Datasheet(HTML) 43 Page - STMicroelectronics

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ELECTRICAL SPECIFICATIONS
Release 1.5 - January 29, 2002
43/93
4.5.6 ISA INTERFACE AC TIMING CHARACTERISTICS
Table 4-7 and Table 4-13 list the AC characteris-
tics of the ISA interface.
Figure 4-7 ISA Cycle (ref Table 4-13)
Note 1: Stands for SMEMR#, SMEMW#, MEMR#, MEMW#, IOR# & IOW#.
The clock has not been represented as it is dependent on the ISA Slave mode.
Valid AENx
Valid Address
Valid Address, SBHE*
V.Data
VALID DATA
54
28
26
64
59
58
55
28
23
61
48
47
26
23
57
27
24
42
41
10
11
34
33
3
22
56
29
25
9
18
2
12
38
37
15
14
13
12
ALE
AEN
LA [23:17]
SA [19:0]
CONTROL (Note 1)
IOCS16#
MCS16#
IOCHRDY
READ DATA
WRITE DATA
Table 4-13. ISA Bus AC Timing
Name
Parameter
Min
Max
Units
2
LA[23:17] valid before ALE# negated
5T
Cycles
3
LA[23:17] valid before MEMR#, MEMW# asserted
3a Memory access to 16-bit ISA Slave
5T
Cycles
3b Memory access to 8-bit ISA Slave
5T
Cycles
9
SA[19:0] & SBHE valid before ALE# negated
1T
Cycles
10
SA[19:0] & SBHE valid before MEMR#, MEMW# asserted
10a Memory access to 16-bit ISA Slave
2T
Cycles
10b Memory access to 8-bit ISA Slave
2T
Cycles
10
SA[19:0] & SHBE valid before SMEMR#, SMEMW# asserted
10c Memory access to 16-bit ISA Slave
2T
Cycle
Note: The signal numbering refers to Table 4-7


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