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STPC4EDBI Datasheet(PDF) 2 Page - STMicroelectronics

Part No. STPC4EDBI
Description  X86 Core PC Compatible Information Appliance System-on-Chip
Download  93 Pages
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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STPC4EDBI Datasheet(HTML) 2 Page - STMicroelectronics

 
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STPC
® CONSUMER-II
2/93
Release 1.5 - January 29, 2002
s
X86 Processor core
s
Fully static 32-bit five-stage pipeline, x86
processor fully PC compatible.
s
Can access up to 4 GB of external memory.
s
8 Kbyte unified instruction and data cache
with write back and write through capability.
s
Parallel processing integral floating point unit,
with automatic power down.
s
Runs up to 100 MHz (x1) or 133 MHz (x2).
s
Fully static design for dynamic clock control.
s
Low power and system management modes.
s
Optimized design for 2.5 V operation.
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SDRAM Controller
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64-bit data bus.
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Up to 100 MHz SDRAM clock speed.
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Integrated system memory, graphic frame
memory and video frame memory.
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Supports 2 MB up to 128 MB system
memory.
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Supports 16-, 64-, and 128-Mbit SDRAMs.
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Supports 8, 16, 32, 64, and 128 MB DIMMs.
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Supports buffered, non buffered, and
registered DIMMs
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Four-line write buffers for CPU to SDRAM
and PCI to SDRAM cycles.
s
Four-line read prefetch buffers for PCI
masters.
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Programmable latency
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Programmable timing for SDRAM
parameters.
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Supports -8, -10, -12, -13, -15 memory parts
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Supports memory hole between 1 MB and
8 MB for PCI/ISA busses.
s
2D Graphics Controller
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64-bit windows accelerator.
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Backward compatibility to SVGA standards.
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Hardware acceleration for text, bitblts,
transparent blts and fills.
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Up to 64 x 64 bit graphics hardware cursor.
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Up to 4MB long linear frame buffer.
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8-, 16-, 24- and 32-bit pixels.
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Drivers availables for various OSes.
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CRT Controller
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Integrated 135 MHz triple RAMDAC allowing
for 1280 x 1024 x 75 Hz display.
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Requires external frequency synthesizer and
reference sources.
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8-bit, 16-bit, 24-bit pixels.
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Interlaced or non-interlaced output.
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Requires no external frequency synthesizer.
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Requires only external reference source.
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Video Input port
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Accepts video inputs in ITU-R 601 mode.
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Optional 2:1 decimator
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Stores captured video in off setting area of
the onboard frame buffer.
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Video pass through to the TV output for full
screen video images.
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HSYNC and B/T generation or lock onto
external video timing source.
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Video Pipeline
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Two-tap interpolative horizontal filter.
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Two-tap interpolative vertical filter.
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Colour space conversion (RGB to YUV and
YUV to RGB).
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Programmable window size.
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Chroma and colour keying for integrated
video overlay.
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Video Output
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NTSC-M; PAL-B, D, G, H, I, M, N encoding.
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ITU-R 601 encoding with programmable
colour subcarrier frequencies.
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ITU-R 656 video output signal interface.
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Four analog outputs in two configurations:
- R,G,B + CVBS
- C,YS,CVBS1 + CVBS2
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Flicker-free interlaced output.
s
Programmable two tap filter with gamma
correction or three tap flicker filter.
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Interlaced or non-interlaced operation mode.
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Progressive to interlaced scan converter.
s
Cross colour reduction by specific trap
filtering on luma within CVBS flow.
s
Power down mode available on each DAC.


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