 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
STPC4EDBI Datasheet(PDF) 16 Page - STMicroelectronics |
|
||||||||||||||||||||||||||||||
STPC4EDBI Datasheet(HTML) 16 Page - STMicroelectronics |
|
|
16 / 93 page 
PIN DESCRIPTION 16/93 Release 1.5 - January 29, 2002 2.2. SIGNAL DESCRIPTIONS 2.2.1. BASIC CLOCKS AND RESETS SYSRSTI# System Reset/Power good. This input is low when the reset switch is depressed. Otherwise, it reflects the power supply power good signal. This input is asynchronous to all clocks, and acts as a negative active reset. The reset circuit initiates a hard reset on the rising edge of this signal. SYSRSTO# Reset Output to System. This is the system reset signal and is used to reset the rest of the components (not on Host bus) in the system. The ISA bus reset is an externally inverted buffered version of this output and the PCI bus reset is an externally buffered version of this output. XTALI 14.3 MHz Crystal Input XTALO 14.3 MHz Crystal Output. These pins are provided for the connection of an external 14.318 MHz crystal to provide the reference clock for the internal frequency synthesizer, from which all other clock signals are generated. The 14.318 MHz series-cut fundamental (not overtone) mode quartz crystal must have an Equivalent Series Resistance (ESR, sometimes referred to as Rm) of less then 50 Ohms (typically 8 Ohms) and a shunt capacitance (Co) of less than 7 pF. Balance capacitors of 16 pF should also be added, one connected to each pin. In the event of an external oscillator providing the master clock signal to the STPC Consumer-II device, the LVTTL signal should be connected to XTALI. HCLK Host Clock. This clock supplies the CPU and the host related blocks. This clock can be doubled inside the CPU and is intended to operate in the range of 25 MHz to 100 MHz. This clock is generated internally from a PLL but can be driven directly from the external system. DEV_CLK 24 MHz Peripheral Clock. This 24 MHz signal is provided as a convenience for the system integration of a Floppy Disk driver function in an external chip. DCLK 135 MHz Dot Clock. This is the dot clock, which drives graphics display cycles. Its frequency can go from 8 MHz (using internal PLL) up to 135 MHz, and it is required to have a worst case duty cycle of 60-40. This signal is driven either by the internal pll (VGA) or by an external 27 MHz oscillator (when the composite video output is enabled). The direction can be controlled by a strap option or an internal register bit. 2.2.2. SDRAM CONTROLLER MCLKO Memory Clock Output. This clock is driving the DIMMs on board and is generated from an internal PLL. The default value is 66 MHz. MCLKI Memory Clock Input. This clock is driving the SDRAM controller, the graphics engine and display controller. This input should be a buffered version of the MCLKO signal with the track lengths between the buffer and the pin matched with the track lengths between the buffer and the DIMMs. CS#[1:0] Chip Select These signals are used to disable or enable device operation by masking or enabling all SDRAM inputs except MCLK, CKE, and DQM. CS#[2]/MA[11] Chip Select/Bank Address This pin is CS#[2] in the case when 16-Mbit devices are used. For all other densities, it becomes MA[11]. CS#[3]/MA[12]/BA[1] Chip Select/Memory Address/Bank Address This pin is CS#[3] in the case when 16-Mbit devices are used. For all other densities, it becomes MA[12] when two internal banks devices are used and BA[1] when four internal bank devices are used. MA[10:0] Memory Address. Multiplexed row and column address lines. BA[0] Memory Bank Address. MD[63:0] Memory Data. This is the 64-bit memory data bus. MD[40-0] are read by the device strap option registers during rising edge of SYSRSTI#. RAS#[1:0] Row Address Strobe. There are two active-low row address strobe output signals. The RAS# signals drive the memory devices directly without any external buffering. CAS#[1:0] Column Address Strobe. There are two active-low column address strobe output signals. The CAS# signals drive the memory devices directly without any external buffering. MWE# Write Enable. Write enable specifies whether the memory access is a read (MWE# = H) or a write (MWE# = L). DQM#[7:0] Data Mask. Makes data output Hi-Z after the clock and masks the SDRAM outputs. Blocks SDRAM data input when DQM active. 2.2.3. PCI CONTROLLER PCI_CLKI 33 MHz PCI Input Clock. This signal is the PCI bus clock input and should be driven from the PCI_CLKO pin. |
English ▼
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
