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STPC4EDBI Datasheet(PDF) 81 Page - STMicroelectronics |
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STPC4EDBI Datasheet(HTML) 81 Page - STMicroelectronics |
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81 / 93 page 
DESIGN GUIDELINES Release 1.5 - January 29, 2002 81/93 6.4.4. PCI INTERFACE 6.4.4.1. Introduction In order to achieve a PCI interface which work at clock frequencies up to 33MHz, careful consideration has to be given to the timing of the interface with all the various electrical and physical constraints taken into consideration. 6.4.4.2. PCI Clocking Scheme The PCI Clocking Scheme deserves a special mention here. Basically the PCI clock (PCICLKO) is generated on-chip from HCLK through a programmable delay line and a clock divider. The nominal frequency is 33MHz. This clock must be looped to PCICLKI and goes to the internal South Bridge through a deskewer. On the contrary, the internal North Bridge is clocked by HCLK, putting some additionnal constraints on T0 and T1. Figure 6-23. Clock Scheme HCLK PLL 1/2 1/3 1/4 clock Strap Options PCICLKO T1 PCICLKI HCLK AD[31:0] South North Deskewer MUX T0 T2 delay STPC MD[30:27] MD[17,4] MD[7:6] Bridge Bridge |
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