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STPC4EDBI Datasheet(PDF) 78 Page - STMicroelectronics

Part No. STPC4EDBI
Description  X86 Core PC Compatible Information Appliance System-on-Chip
Download  93 Pages
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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STPC4EDBI Datasheet(HTML) 78 Page - STMicroelectronics

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DESIGN GUIDELINES
78/93
Release 1.5 - January 29, 2002
6.4.3. MEMORY INTERFACE
6.4.3.1. Introduction
In order to achieve SDRAM memory interfaces
which work at clock frequencies of 100 MHz and
above, careful consideration has to be given to the
timing of the interface with all the various electrical
and physical constraints taken into consideration.
The guidelines described below are related to
SDRAM components on DIMM modules. For
applications where the memories are directly
soldered to the motherboard, the PCB should be
laid out such that the trace lengths fit within the
constraints shown here. The traces could be
slightly shorter since the extra routing on the
DIMM PCB is no longer present but it is then up to
the user to verify the timings.
6.4.3.2. SDRAM Clocking Scheme
The SDRAM Clocking Scheme deserves a special
mention here. Basically the memory clock is
generated on-chip through a PLL and goes
directly to the MCLKO output pin of the STPC. The
nominal frequency is 100 MHz. Because of the
high load presented to the MCLK on the board by
the DIMMs it is recommended to rebuffer the
MCLKO signal on the board and balance the skew
to the clock ports of the different DIMMs and the
MCLKI input pin of STPC.
6.4.3.3. Board Layout Issues
The physical layout of the motherboard PCB
assumed in this presentation is as shown in Figure
6-19. Because all of the memory interface signal
balls are located in the same region of the STPC
device, it is possible to orientate the device to
reduce the trace lengths. The worst case routing
length to the DIMM1 is estimated to be 100 mm.
Solid power and ground planes are a must in order
to provide good return paths for the signals and to
reduce EMI and noise. Also there should be ample
high frequency decoupling between the power
and ground planes to provide a low impedance
path between the planes for the return paths for
signal routings which change layers. If possible,
the traces should be routed adjacent to the same
power or ground plane for the length of the trace.
For the SDRAM interface, the most critical signal
is the clock. Any skew between the clocks at the
SDRAM components and the memory controller
will impact the timing budget. In order to get well
matched
clocks
at
all
components
it
is
recommended that all the DIMM clock pins, STPC
Figure 6-18. Clock Scheme
MCLKI
MCLKO
PLL
PLL
MA[ ] + Control
MD[63:0]
SDRAM
CONTROLLER


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