STPC12HEYI datasheet(94/111 Pages) STMICROELECTRONICS

Part #	STPC12HEYI

Description	X86 Core PC Compatible System-on-Chip for Terminals

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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94 / 111 page

DESIGN GUIDELINES

94/111

Issue 1.0 - July 24, 2002

memory clock input (MCLKI) and any other

component

using

the

memory

clock

are

individually driven from a low skew clock driver

with matched routing lengths. In other words, all

clock line lengths that go from the buffer to the

memory chips (MCLKx) and from the buffer to the

STPC (MCLKI) must be identical.

This is shown in Figure 6-23.

Figure 6-22. DIMM placement

DIMM2

DIMM1

STPC

35mm

15mm

10mm

116mm

SDRAM I/F

Figure 6-23. Clock Routing

MCLKO

DIMM CKn input

STPC MCLKI

DIMM CKn input

Low skew clock driver:

L

L+75mm*

20pF

* No additional 75mm when SDRAM directly soldered on board

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