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STPIC44L02 Datasheet(PDF) 1 Page - STMicroelectronics |
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STPIC44L02 Datasheet(HTML) 1 Page - STMicroelectronics |
1 / 21 page 1/21 July 2003 s 4-CHANNEL SERIAL-IN PARALLEL-IN LOW SIDE PRE-FET DRIVER s DEVICES ARE CASCADABLE s INTERNAL 55V INDUCTIVE LOAD CLAMP AND VGS PROTECTION CLAMP FOR EXTERNAL POWER FETS s INDEPENDENT SHORTED-LOAD AND SHORT-TO-BATTERY FAULT DETECTION ON ALL GATE TERMINALS s INDEPENDENT OFF-STATE OPEN-LOAD FAULT SENSE s OVER-BATTERY-VOLTAGE LOCKOUT PROTECTION AND FAULT REPORTING s UNDER-BATTERY VOLTAGE LOCKOUT PROTECTION s ASYNCRONOUS OPEN-GATE FAULT FLAG s DEVICE OUTPUT CAN BE WIRED OR WITH MULTIPLE DEVICES s FAULT STATUS RETURNED THROUGH SERIAL OUTPUT TERMINAL s INTERNAL GLOBAL POWER-ON RESET OF DEVICE AND EXTERNAL RESET TERMINAL s HIGH IMPEDANCE CMOS COMPATIBLE INPUTS WITH HYSTERESIS s TRANSITION FROM THE GATE OUTPUT TO A LOW DUTY CYCLE PWM MODE WHEN A SHORTEDLOADFAULT OCCURS DESCRIPTION The STPIC44L02 is a low-side predriver that provides serial and parallel input interfaces to control four external FET power switches. It is mainly designed to provide low-frequency switching, inductive load applications such as solenoids and relays. Fault status is available in a serial-data format. Each driver channel has independent off-state open-load detection and on-state shorted load short to battery detection. The STPIC44L02 offers a battery over voltage and undervoltage detection and shutdown. If a fault occurs while using the STPIC44L02, the channel transitates into a low duty cycle, pulse width modulated (PWM) signal as long as the fault is present. These devices provide control of output channels through a serial input interface or a parallel input interface. A command to enable the output from either interface enables the respective channels gate output to the external FET. The serial interface is recommended when the number of signals between the control device and the predriver are minimized and the speed of operation is not critical. In applications where the predriver must respond very quickly or asynchronously, the parallel input interface is recommended. For serial operation, the control device must transitate CS from high to low to activate the serial input interface. When this occurs, SDO, is enabled, fault data is latched into the serial interface, and the fault flag is refreshed. Data is clocked into the serial registers on low to high transitions of SCLK through SDI. Each string of data must consist of at least four bits of data. In applications where multiple devices are cascaded together, the string of data must consist of four bits for each device. A high data bit turns the respective output channel on and a low data bit turns it off. Fault data for the device is clocked out of SDO as serial input data is clocked into the device. Fault data consists of fault flags for shorted load and open load flags (bits 0-3) for each of the four output channels. Fault register bits are set or cleared asynchronously to reflect the current state of the hardware. A fault must be present when CS is transitated from high to low to be captured and reported in the serial fault data. New faults cannot be captured in the serial register when CS is low. CS must be transitated high after all of the serial data has been clocked into the device. A low to high transition of CS transfers the last four bits of serial data to the STPIC44L02 4 CHANNEL SERIAL AND PARALLEL LOW SIDE PRE-FET DRIVER SOP |
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