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STPCC5HEBI Datasheet(PDF) 19 Page - STMicroelectronics |
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STPCC5HEBI Datasheet(HTML) 19 Page - STMicroelectronics |
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19 / 93 page  PIN DESCRIPTION Release 1.5 - January 29, 2002 19/93 ISACLK and ISACLKX2 as the input selection strobes. DACK_ENC[2:0] DMA Acknowledge. These are the ISA bus DMA acknowledge signals. They are encoded by the STPC Consumer-II before output and should be decoded externally using ISACLK and ISACLKX2 as the control strobes. TC ISA Terminal Count. This is the terminal count output of the DMA controller and is connected to the TC line of the ISA bus. It is asserted during the last DMA transfer, when the byte count expires. RTCAS Real time clock address strobe. This sig- nal is asserted for any I/O write to port 70H. RMRTCCS# ROM/Real Time clock chip select. This signal is asserted if a ROM access is decoded during a memory cycle. It should be combined with MEMR# or MEMW# signals to properly access the ROM. During a IO cycle, this signal is asserted if access to the Real Time Clock (RTC) is decoded. It should be combined with IOR or IOW# signals to properly access the real time clock. KBCS# Keyboard Chip Select. This signal is asserted if a keyboard access is decoded during a I/O cycle. RTCRW# Real Time Clock RW. This pin is a multi- function pin. When ISAOE# is active, this signal is used as RTCRW#. This signal is asserted for any I/O write to port 71H. RTCDS# Real Time Clock DS. This pin is a multi- function pin. When ISAOE# is active, this signal is used as RTCDS#. This signal is asserted for any I/ O read to port 71H. Its polarity complies with the DS pin of the MT48T86 RTC device when configured with Intel timings. Note: RMRTCCS#, KBCS#, RTCRW# and RTCDS# signals must be ORed externally with ISAOE# and then connected to the external device. An LS244 or equivalent function can be used if OE# is connected to ISAOE# and the output is provided with a weak pull-up resistor as shown in Figure 6-10. 2.2.5. LOCAL BUS INTERFACE PA[23:0] Address Bus Output. PD[15:0] Data Bus. This is the 16-bit data bus. D[7:0] is the LSB and PD[15:8] is the MSB. PRD#[1:0] Read Control output. PRD0# is used to read the LSB and PRD1# to read the MSB. PWR#[1:0] Write Control output. PWR0# is used to write the LSB and PWR1# to write the MSB. PRDY Data Ready input. This signal is used to create wait states on the bus. When high, it completes the current cycle. FCS#[1:0] Flash Chip Select output. These are the Programmable Chip Select signals for up to two banks of Flash memory. IOCS#[3:0] I/O Chip Select output. These are the Programmable Chip Select signals for up to four external I/O devices. 2.2.6. IDE INTERFACE SCS1#, SCS3# Secondary Chip Select. These signals are used as the active high secondary master & slave IDE chip select signals. These signals must be externally ANDed with the ISAOE# signal before driving the IDE devices to guarantee it is active only when ISA bus is idle. DA[2:0] Address. These signals are connected to DA[2:0] of IDE devices directly or through a buffer. If the toggling of signals are to be masked during ISA bus cycles, they can be externally ORed with ISAOE# before being connected to the IDE devices. DD[15:0] Databus. When the IDE bus is active, they serve as IDE signals DD[11:0]. IDE devices are connected to SA[19:8] directly and ISA bus is connected to these pins through two LS245 transceivers as described in Figure 6-10. PCS1#, PCS3# Primary Chip Select. These signals are used as the active high primary master & slave IDE chip select signals. These signals must be externally ANDed with the ISAOE# signal before driving the IDE devices to guarantee it is active only when ISA bus is idle. DIORDY Busy/Ready. This pin serves as IDE signal DIORDY. PIRQ Primary Interrupt Request. SIRQ Secondary Interrupt Request. Interrupt request from IDE channels. PDRQ Primary DMA Request. SDRQ Secondary DMA Request. DMA request from IDE channels. PDACK# Primary DMA Acknowledge. SDACK# Secondary DMA Acknowledge. DMA acknowledge to IDE channels. PDIOR#, PDIOW# Primary I/O Read & Write. SDIOR#, SDIOW# Secondary I/O Read & Write. Primary & Secondary channel read & write. |
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