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STPCELITE Datasheet(PDF) 1 Page - STMicroelectronics |
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STPCELITE Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 87 page 
STPC ® ELITE X86 Core General Purpose PC Compatible System - on - Chip Release 1.3 - January 29, 2002 1/87 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Logic Diagram s POWERFUL X86 PROCESSOR s 64-BIT SDRAM CONTROLLER AT 100MHz s INTEGRATED PCI NORTH / SOUTH BRIDGE CONTROLLER s ISA MASTER / SLAVE / DMA s 16-BIT LOCAL BUS INTERFACE FOR LOW COST AND EMBEDDED APPLICATIONS s EIDE CONTROLLER s INTEGRATED PERIPHERAL CONTROLLER - DMA CONTROLLER - INTERRUPT CONTROLLER - TIMER / COUNTERS s POWER MANAGEMENT UNIT s I²C INTERFACE s 16 ENHANCED GENERAL PURPOSE I/Os. s JTAG IEEE1149.1 s PROGRAMMABLE OUTPUT CLOCK UP TO 135MHz s COMMERCIAL AND INDUSTRIAL TEM- PERATURE RANGES DESCRIPTION The STPC Elite integrates a fully static x86 processor up to 133 MHz, fully compatible with standard x86 processors, and combines it with powerful chipset to provide a general purpose PC compatible subsystem on a single device. The device is packaged in a 388 Ball Grid Array (PBGA). The STPC Elite has a low voltage operation with VCORE = 2.5V and has 5V tolerant I/Os (3.3V output levels). PBGA388 ST PC EL ITE x86 Core Host I/F SDRAM CONTROL PCI I/F PCI ISA I/F EIDE ctrl PCI I/F ISA BUS EIDE L.B. I/F LOCAL BUS IPC JTAG PMU |
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