© 2008 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FAN6751MR • Rev. 1.0.0

3

Marking Information

Figure 3. Top Mark

Pin Configuration

Figure 4. Pin Configuration (Top View)

Pin Definitions

Pin #

Name

Description

1

GND

Ground.

2

FB

The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is

determined in response to the signal on this pin and the current-sense signal on the SENSE pin.

3

NC

No connection.

4

HV

For startup, this pin is pulled high to the line input or bulk capacitor via resistors.

5

VIN

Line-voltage detection. The line-voltage detection is used for brownout protection with

hysteresis. Constant output power limit over universal AC input range is also achieved using this

VIN pin. It is suggested to add a low pass filter to filter out line ripple on bulk capacitor. VIN

pulling high triggers latch protection.

6

SENSE

Current sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle

current limiting.

7

VDD

OVP trigger point.

8

GATE

The totem-pole output driver. Soft-driving waveform is implemented for improved EMI.

1

2

3

4

SOP-8

8

7

6

5

GND

FB

NC

HV

GATE

VDD

SENSE

VIN

ZXYTT

6751MR

TPM

F: Fairchild logo

Z: Plant code

X: 1 digit year code

Y: 1 digit week code

TT: 2 digits die run code

T: Package type (N:DIP, M:SOP)

P: Y=Green package

M: Manufacture flow code