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STPCI2GDY Datasheet(PDF) 55 Page - STMicroelectronics

Part No. STPCI2GDY
Description  X86 Core PC Compatible System-on-Chip for Terminals
Download  111 Pages
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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STPCI2GDY Datasheet(HTML) 55 Page - STMicroelectronics

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ELECTRICAL SPECIFICATIONS
Issue 1.0 - July 24, 2002
55/111
10d Memory access to 8-bit ISA Slave
2T
Cycle
10e
SA[19:0] & SBHE valid before IOR#, IOW# asserted
2T
Cycles
11
ISACLK2X to IOW# valid
11a Memory access to 16-bit ISA Slave - 2BCLK
2T
Cycles
11b Memory access to 16-bit ISA Slave - Standard 3BCLK
2T
Cycles
11c Memory access to 16-bit ISA Slave - 4BCLK
2T
Cycles
11d Memory access to 8-bit ISA Slave - 2BCLK
2T
Cycles
11e
Memory access to 8-bit ISA Slave - Standard 3BCLK
2T
Cycles
12
ALE# asserted before ALE# negated
1T
Cycles
13
ALE# asserted before MEMR#, MEMW# asserted
13a Memory Access to 16-bit ISA Slave
2T
Cycles
13b Memory Access to 8-bit ISA Slave
2T
Cycles
13
ALE# asserted before SMEMR#, SMEMW# asserted
13c Memory Access to 16-bit ISA Slave
2T
Cycles
13d Memory Access to 8-bit ISA Slave
2T
Cycles
13e
ALE# asserted before IOR#, IOW# asserted
2T
Cycles
14
ALE# asserted before AL[23:17]
14a Non compressed
15T
Cycles
14b Compressed
15T
Cycles
15
ALE# asserted before MEMR#, MEMW#, SMEMR#, SMEMW# negated
15a Memory Access to 16-bit ISA Slave- 4 BCLK
11T
Cycles
15e Memory Access to 8-bit ISA Slave- Standard Cycle
11T
Cycles
18a
ALE# negated before LA[23:17] invalid (non compressed)
14T
Cycles
18a
ALE# negated before LA[23:17] invalid (compressed)
14T
Cycles
22
MEMR#, MEMW# asserted before LA[23:17]
22a Memory access to 16-bit ISA Slave.
13T
Cycles
22b Memory access to 8-bit ISA Slave.
13T
Cycles
23
MEMR#, MEMW# asserted before MEMR#, MEMW# negated
23b Memory access to 16-bit ISA Slave Standard cycle
9T
Cycles
23e Memory access to 8-bit ISA Slave Standard cycle
9T
Cycles
23
SMEMR#, SMEMW# asserted before SMEMR#, SMEMW# negated
23h Memory access to 16-bit ISA Slave Standard cycle
9T
Cycles
23l Memory access to 16-bit ISA Slave Standard cycle
9T
Cycles
23
IOR#, IOW# asserted before IOR#, IOW# negated
23o Memory access to 16-bit ISA Slave Standard cycle
9T
Cycles
23r Memory access to 8-bit ISA Slave Standard cycle
9T
Cycles
24
MEMR#, MEMW# asserted before SA[19:0]
24b Memory access to 16-bit ISA Slave Standard cycle
10T
Cycles
24d Memory access to 8-bit ISA Slave - 3BLCK
10T
Cycles
24e Memory access to 8-bit ISA Slave Standard cycle
10T
Cycles
24f Memory access to 8-bit ISA Slave - 7BCLK
10T
Cycles
24
SMEMR#, SMEMW# asserted before SA[19:0]
24h
Memory access to 16-bit ISA Slave Standard cycle
10T
Cycles
24i
Memory access to 16-bit ISA Slave - 4BCLK
10T
Cycles
24k
Memory access to 8-bit ISA Slave - 3BCLK
10T
Cycles
24l
Memory access to 8-bit ISA Slave Standard cycle
10T
Cycles
Table 4-14. ISA Bus AC Timing
Name
Parameter
Min
Max
Units
Note: The signal numbering refers to Table 4-8


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