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STPCI2GDY Datasheet(PDF) 37 Page - STMicroelectronics

Part No. STPCI2GDY
Description  X86 Core PC Compatible System-on-Chip for Terminals
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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STPCI2GDY Datasheet(HTML) 37 Page - STMicroelectronics

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STRAP OPTION
Issue 1.0 - July 24, 2002
37/111
3.1.3. HCLK PLL STRAP REGISTER
This register is read only.
HCLK_STRAP0
Access = 0022h/0023h
Regoffset =05Fh
76543210
RSV
MD[26]
MD[25]
MD[24]
RSV
This register defaults to the values sampled on the MD pins after reset
Bit Number Sampled
Mnemonic
Description
Bits 7-6
Rsv
These bits are fixed to ‘0’
Bits 5-3
MD[26:24]
These pins reflect the values sampled on MD[26:24] pins respectively
and control the Host clock frequency synthesizer as shown in Table 3-1
Bits 2-0
Rsv
Reserved
Table 3-1. HCLK Frequency Configuration
MD[3]
MD[2]
MD[26]
MD[25]
MD[24]
HCLK Speed
00
000
25 MHz
00
001
50 MHz
00
010
60 MHz
00
011
66 MHz
All other settings are reserved


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