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STPCI2GDY Datasheet(PDF) 24 Page - STMicroelectronics

Part No. STPCI2GDY
Description  X86 Core PC Compatible System-on-Chip for Terminals
Download  111 Pages
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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STPCI2GDY Datasheet(HTML) 24 Page - STMicroelectronics

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PIN DESCRIPTION
24/111
Issue 1.0 - July 24, 2002
RSET Resistor Current Set. This is the reference
current input to the RAMDAC. Used to set the full-
scale output of the RAMDAC.
COMP Compensation. This is the RAMDAC
compensation pin. Normally, an external capacitor
(typically 10nF) is connected between this pin and
VDD to damp oscillations.
DDC[1:0] Direct Data Channel Serial Link. These
bidirectional pins are connected to CRTC register
3Fh to implement DDC capabilities. They conform
to I2C electrical specifications, they have open-
collector output drivers which are internally
connected to VDD through pull-up resistors.
They can instead be used for accessing I²C
devices on board. DDC1 and DDC0 correspond to
SCL and SDA respectively.
2.2.10. VIDEO INTERFACE
VCLK Pixel Clock Input.This signal is used to
synchronise data being transferred from an
external video device to either the frame buffer, or
alternatively out the TV output in bypass mode.
This pin can be sourced from STPC if no external
VCLK is detected, or can be input from an external
video clock source.
VIN[7:0]
YUV Video Data Input ITU-R 601 or 656.
Time
multiplexed
4:2:2
luminance
and
chrominance data as defined in ITU-R Rec601-2
and Rec656 (except for TTL input levels). This bus
typically carries a stream of Cb,Y,Cr,Y digital
video at VCLK frequency, clocked on the rising
edge (by default) of VCLK.
VCS
Line synchronisation Input. This is the
horizontal synchronisation
of
the
incomming
CCIR601 video.
The signal is synchronous to rising edge of VCLK.
ODD_EVEN
Frame Synchronisation Output. This
is the vertical synchronisation of the incomming
CCIR601 video.
The signal is synchronous to rising edge of VCLK.
The default polarity for this pin is:
- odd (not-top) field: LOW level
- even (bottom) field: HIGH level
2.2.11. TFT INTERFACE SIGNALS
The TFT (Thin Film Transistor) interface converts
signals from the CRT controller into control signals
for an external TFT Flat Panel. The signals are
listed below.
TFTFRAME, Vertical Sync. pulse Output.
TFTLINE, Horizontal Sync. Pulse Output.
TFTDE, Data Enable.
TFTR5-0, Red Output.
TFTG5-0, Green Output.
TFTB5-0, Blue Output.
TFTENVDD, Enable VDD of Flat Panel.
TFTENVCC, Enable VCC of Flat Panel.
PWM PWM Back-Light Control. This PWM is
clocked by the PCI clock.
TFTDCLK, Dot clock for the Flat Panel.
2.2.12. USB INTERFACE
OC OVER CURRENT DETECT This signal is
used to monitor the status of the USB power
supply lines of both devices. USB port are
disabled when OC signal is asserted.
USBDPL0, USBDMNS0
UNIVERSAL SERIAL
BUS DATA 0 This signal pair comprises the
differential data signal for USB port 0.
USBDPL1, USBDMNS1 UNIVERSAL SERIAL
BUS PORT 1 This signal pair comprises the
differential data signal for USB port 1.
POWERON USB power supply lines
2.2.13. SERIAL INTERFACE
RXD0, RXD1 Serial Input. Data is clocked in using
RCLK/16.
TXD0, TXD1 Serial Output. Data is clocked out
using TCLK/16 (TCLK=BAUD#).
DCD0#, DCD1# Input Data carrier detect.
RI0#, RI1# Input Ring indicator.
DSR0#, DSR1# Input Data set ready.
CTS0#, CTS1# Input Clear to send.
RTS0#, RTS1# Output Request to send.
DTR0#, DTR1# Output Data terminal read.
2.2.14. KEYBOARD/MOUSE INTERFACE
KBCLK, Keyboard Clock line. Keyboard data is
latched by the controller on each negative clock
edge produced on this pin. The keyboard can be
disabled by pulling this pin low by software control.
KBDATA,
Keyboard Data Line. 11-bits of data are
shifted serially through this line when data is being
transferred. Data is synchronised to KBCLK.


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