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STPCI2GDY Datasheet(PDF) 23 Page - STMicroelectronics

Part No. STPCI2GDY
Description  X86 Core PC Compatible System-on-Chip for Terminals
Download  111 Pages
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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STPCI2GDY Datasheet(HTML) 23 Page - STMicroelectronics

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PIN DESCRIPTION
Issue 1.0 - July 24, 2002
23/111
used to control voltages (VPP1, VPP2 and VCC)
to a PC Card socket. Also see Section 13.7.5.
GPI# General Purpose Input. This signal is
hardwired to 1.
2.2.6. LOCAL BUS
PA[24:0] Address Bus Output.
PD[15:0] Data Bus. This is the 16-bit data bus.
D[7:0] is the LSB and PD[15:8] is the MSB.
PRD#[1:0] Read Control output. These are
memory and I/O Read signals. PRD0# is used to
read the LSB and PRD1# to read the MSB.
PWR#[1:0] Write Control output. These are
memory and I/O Write signals. PWR0# is used to
write the LSB and PWR1# to write the MSB.
PRDY Data Ready input. This signal is used to
create wait states on the bus. When high, it
completes the current cycle.
FCS#[1:0]
Two Flash Memory Chip Select
outputs. These are the Programmable Chip Select
signals for Flash memory.
IOCS#[7:0] I/O Chip Select output. These are the
Programmable Chip Select signals for up to 4
external I/O devices.
PBE#[1:0] Byte Enable. These are the Byte
enables that identifies on which databus the date
is valid. PBE#[0] corresponds to PD[7:0] and
PBE#[1] corresponds to PD[15:8]. These are
normally used when 8 bit transfers are transfered
across the 16 bit bus.
IRQ_MUX#[3:0]
Multiplexed Interrupt Lines.
2.2.7. IPC
DACK_ENC[2:0] DMA Acknowledge. These are
the ISA bus DMA acknowledge signals. They are
encoded by the STPC Industrial before output and
should be decoded externally using ISACLK and
ISACLKX2 as the control strobes.
DREQ_MUX[1:0]
ISA Bus Multiplexed DMA
Request. These are the ISA bus DMA request
signals.
They
are
to
be
encoded
before
connection to the STPC Industrial using ISACLK
and ISACLKX2 as the input selection strobes.
TC ISA Terminal Count. This is the terminal count
output of the DMA controller and is connected to
the TC line of the ISA bus. It is asserted during the
last DMA transfer, when the Byte count expires.
2.2.8. IDE INTERFACE
DA[2:0] Address. These signals are connected to
DA[2:0] of IDE devices directly or through a buffer.
If the toggling of signals are to be masked during
ISA bus cycles, they can be externally ORed with
ISAOE# before being connected to the IDE
devices.
DD[15:0]
Databus. When the IDE bus is active,
they serve as IDE signals DD[11:0]. IDE devices
are connected to SA[19:8] directly and ISA bus is
connected to these pins through two LS245
transceivers.
PCS1, PCS3, SCS1, SCS3
Primary & Secondary
Chip Selects. These signals are used as the active
high primary and secondary master & slave IDE
chip select signals. These signals must be
externally NANDed with the ISAOE# signal before
driving the IDE devices to guarantee it is active
only when ISA bus is idle. In Local Bus mode, they
just need to be inverted.
DIORDY Busy/Ready. This pin serves as IDE
signal DIORDY.
PIRQ Primary Interrupt Request.
SIRQ Secondary Interrupt Request.
Interrupt request from IDE channels.
PDRQ Primary DMA Request.
SDRQ Secondary DMA Request.
DMA request from IDE channels.
PDACK# Primary DMA Acknowledge.
SDACK# Secondary DMA Acknowledge.
DMA acknowledge to IDE channels.
PDIOR#, PDIOW# Primary I/O Read & Write.
SDIOR#, SDIOW# Secondary I/O Read & Write.
Primary & Secondary channel read & write.
2.2.9. MONITOR INTERFACE
RED, GREEN, BLUE RGB Video Outputs. These
are the 3 analog colour outputs from the
RAMDACs.
These
signals
are
sensitive
to
interference, therefore they need to be properly
shielded.
VSYNC
Vertical Synchronisation Pulse. This is
the vertical synchronization signal from the VGA
controller.
HSYNC Horizontal Synchronisation Pulse. This is
the horizontal synchronization signal from the
VGA controller.
VREF_DAC DAC Voltage reference. This pin is
an input driving the digital to analog converters.
This allows an external voltage reference source
to be used.


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