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STPCI2GDY Datasheet(PDF) 21 Page - STMicroelectronics

Part No. STPCI2GDY
Description  X86 Core PC Compatible System-on-Chip for Terminals
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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STPCI2GDY Datasheet(HTML) 21 Page - STMicroelectronics

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PIN DESCRIPTION
Issue 1.0 - July 24, 2002
21/111
the STPC Atlas. The STPC Atlas monitors this
signal as an input when performing an ISA cycle
on behalf of the host CPU, DMA master or refresh.
ISA masters which do not monitor IOCHRDY are
not guaranteed to work with the STPC Atlas since
the access to the system memory can be
considerably delayed due to CRT refresh or a
write back cycle.
ALE
Address Latch Enable. This is the address
latch enable output of the ISA bus and is asserted
by the STPC Atlas to indicate that LA23-17, SA19-
0, AEN and SBHE# signals are valid. The ALE is
driven high during refresh, DMA master or an ISA
master cycles by the STPC Atlas.
ALE is driven low after reset.
BHE#
System Bus High Enable. This signal, when
asserted, indicates that a data Byte is being
transferred on SD15-8 lines. It is used as an input
when an ISA master owns the bus and is an
output at all other times.
MEMR#
Memory Read. This is the memory read
command signal of the ISA bus. It is used as an
input when an ISA master owns the bus and is an
output at all other times.
The MEMR# signal is active during refresh.
MEMW#
Memory Write. This is the memory write
command signal of the ISA bus. It is used as an
input when an ISA master owns the bus and is an
output at all other times.
SMEMR# System Memory Read. The STPC Atlas
generates SMEMR# signal of the ISA bus only
when the address is below one MByte or the cycle
is a refresh cycle.
SMEMW# System Memory Write. The STPC
Atlas generates SMEMW# signal of the ISA bus
only when the address is below one MByte.
IOR# I/O Read. This is the IO read command
signal of the ISA bus. It is an input when an ISA
master owns the bus and is an output at all other
times.
IOW# I/O Write. This is the IO write command
signal of the ISA bus. It is an input when an ISA
master owns the bus and is an output at all other
times.
MASTER#
Add On Card Owns Bus. This signal is
active when an ISA device has been granted bus
ownership.
MCS16# Memory Chip Select16. This is the
decode of LA23-17 address pins of the ISA
address bus without any qualification of the
command signal lines. MCS16# is always an
input. The STPC Atlas ignores this signal during
IO and refresh cycles.
IOCS16#
IO Chip Select16. This signal is the
decode of SA15-0 address pins of the ISA
address bus without any qualification of the
command signals. The STPC Atlas does not drive
IOCS16# (similar to PC-AT design). An ISA
master access to an internal register of the STPC
Atlas is executed as an extended 8-bit IO cycle.
REF#
Refresh Cycle. This is the refresh command
signal of the ISA bus. It is driven as an output
when the STPC Atlas performs a refresh cycle on
the ISA bus. It is used as an input when an ISA
master owns the bus and is used to trigger a
refresh cycle.
The STPC Atlas performs a pseudo hidden
refresh. It requests the host bus for two host
clocks to drive the refresh address and capture it
in
external
buffers.
The
host bus
is
then
relinquished while the refresh cycle continues on
the ISA bus.
AEN
Address Enable. Address Enable is enabled
when the DMA controller is the bus owner to
indicate that a DMA transfer will occur. The
enabling of the signal indicates to IO devices to
ignore
the
IOR#/IOW#
signal
during
DMA
transfers.
IOCHCK#
IO Channel Check. IO Channel Check
is enabled by any ISA device to signal an error
condition that can not be corrected. NMI signal
becomes active upon seeing IOCHCK# active if
the corresponding bit in Port B is enabled.
GPIOCS#
I/O General Purpose Chip Select 1.
This output signal is used by the external latch on
ISA bus to latch the data on the SD[7:0] bus. The
latch can be use by PMU unit to control the
external peripheral devices to power down or any
other desired function.
RTCRW#
Real Time Clock RW#. This pin is used
as RTCRW#. This signal is asserted for any I/O
write to port 71h.
RTCDS# Real Time Clock DS. This pin is used as
RTCDS#. This signal is asserted for any I/O read
to port 71h. Its polarity complies with the DS pin of
the MT48T86 RTC device when configured with
Intel timings.
RTCAS
Real time clock address strobe. This
signal is asserted for any I/O write to port 70h.
RMRTCCS# ROM/Real Time clock chip select.
This pin is a multi-function pin. This signal is
asserted if a ROM access is decoded during a
memory cycle. It should be combined with
MEMR# or MEMW# signals to properly access the
ROM. During an IO cycle, this signal is asserted if
access to the Real Time Clock (RTC) is decoded.
It should be combined with IOR# or IOW# signals
to properly access the real time clock.


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