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STPCI2GDY Datasheet(PDF) 20 Page - STMicroelectronics

Part No. STPCI2GDY
Description  X86 Core PC Compatible System-on-Chip for Terminals
Download  111 Pages
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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STPCI2GDY Datasheet(HTML) 20 Page - STMicroelectronics

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PIN DESCRIPTION
20/111
Issue 1.0 - July 24, 2002
CAS#[1:0] Column Address Strobe. There are
two active-low column address strobe output
signals. The CAS# signals drive the memory
devices directly without any external buffering.
MWE#
Write Enable. Write enable specifies
whether the memory access is a read (MWE# = H)
or a write (MWE# = L). This single write enable
controls all DRAMs. The MWE# signals drive the
memory devices directly without any external
buffering.
2.2.3. PCI INTERFACE
AD[31:0] PCI Address/Data. This is the 32-bit
multiplexed address and data bus of the PCI. This
bus is driven by the master during the address
phase and data phase of write transactions. It is
driven by the target during data phase of read
transactions.
PBE[3:0]#
Bus Commands/Byte Enables. These
are the multiplexed command and Byte enable
signals of the PCI bus. During the address phase
they define the command and during the data
phase they carry the Byte enable information.
These pins are inputs when a PCI master other
than the STPC Atlas owns the bus and outputs
when the STPC Atlas owns the bus.
FRAME#
Cycle Frame. This is the frame signal of
the PCI bus. It is an input when a PCI master owns
the bus and is an output when STPC Atlas owns
the PCI bus.
TRDY# Target Ready. This is the target ready
signal of the PCI bus. It is driven as an output
when the STPC Atlas is the target of the current
bus transaction. It is used as an input when STPC
Atlas initiates a cycle on the PCI bus.
IRDY#
Initiator Ready. This is the initiator ready
signal of the PCI bus. It is used as an output when
the STPC Atlas initiates a bus cycle on the PCI
bus. It is used as an input during the PCI cycles
targeted to the STPC Atlas to determine when the
current PCI master is ready to complete the
current transaction.
STOP#
Stop Transaction. STOP# is used to
implement the disconnect, retry and abort protocol
of the PCI bus. It is used as an input for the bus
cycles initiated by the STPC Atlas and is used as
an output when a PCI master cycle is targeted to
the STPC Atlas.
DEVSEL#
Device Select. This signal is used as
an input when the STPC Atlas initiates a bus cycle
on the PCI bus to determine if a PCI slave device
has decoded itself to be the target of the current
transaction. It is asserted as an output either when
the STPC Atlas is the target of the current PCI
transaction or when no other device asserts
DEVSEL# prior to the subtractive decode phase of
the current PCI transaction.
PAR
Parity Signal Transactions. This is the parity
signal of the PCI bus. This signal is used to
guarantee
even
parity
across
AD[31:0],
CBE[3:0]#, and PAR. This signal is driven by the
master during the address phase and data phase
of write transactions. It is driven by the target
during data phase of read transactions. (Its
assertion is identical to that of the AD bus delayed
by one PCI clock cycle)
PERR#
Parity Error
SERR# System Error. This is the system error
signal of the PCI bus. It may, if enabled, be
asserted for one PCI clock cycle if target aborts a
STPC Atlas initiated PCI transaction. Its assertion
by either the STPC Atlas or by another PCI bus
agent will trigger the assertion of NMI to the host
CPU. This is an open drain output.
LOCK#
PCI Lock. This is the lock signal of the PCI
bus and is used to implement the exclusive bus
operations when acting as a PCI target agent.
PCI_REQ#[2:0] PCI Request. These pins are the
three external PCI master request pins. They
indicates to the PCI arbiter that the external
agents desire use of the bus.
PCI_GNT#[2:0]
PCI Grant. These pins indicate
that the PCI bus has been granted to the master
requesting it on its PCI_REQ#.
PCI_INT#[3:0] PCI Interrupt Request. These are
the PCI bus interrupt signals. They are to be
encoded before connection to the STPC Atlas
using ISACLK and ISACLKX2 as the input
selection strobes.
2.2.4. ISA BUS INTERFACE
LA[23:17] Unlatched Address. These unlatched
ISA Bus pins address bits 23-17 on 16-bit devices.
When the ISA bus is accessed by any cycle
initiated from the PCI bus, these pins are in output
mode. When an ISA bus master owns the bus,
these pins are tristated.
SA[19:0]
Unlatched Address. These are the 20
low bits of the system address bus of ISA. These
pins are used as an input when an ISA bus master
owns the bus and are outputs at all other times.
SD[15:0] I/O Data Bus (ISA). These are the
external ISA databus pins.
IOCHRDY IO Channel Ready. IOCHRDY is the IO
channel ready signal of the ISA bus and is driven
as an output in response to an ISA master cycle
targeted to the host bus or an internal register of


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