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STPCI2GDY Datasheet(PDF) 19 Page - STMicroelectronics

Part No. STPCI2GDY
Description  X86 Core PC Compatible System-on-Chip for Terminals
Download  111 Pages
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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STPCI2GDY Datasheet(HTML) 19 Page - STMicroelectronics

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PIN DESCRIPTION
Issue 1.0 - July 24, 2002
19/111
2.2. SIGNAL DESCRIPTIONS
2.2.1. BASIC CLOCKS AND RESETS
SYSRSTI# System Reset/Power good. This input
is low when the reset switch is depressed.
Otherwise, it reflects the power supply’s power
good signal. PWGD is asynchronous to all clocks,
and acts as a negative active reset. The reset
circuit initiates a hard reset on the rising edge of
PWGD.
Note that while Reset is being asserted, the
signals on the device pins are in an unknown
state.
SYSRSTO#
Reset Output to System. This is the
system reset signal and is used to reset the rest of
the components (not on Host bus) in the system.
The ISA bus reset is an externally inverted
buffered version of this output and the PCI bus
reset is an externally buffered version of this
output.
XTALI
14.3 MHz Crystal Input
XTALO 14.3 MHz Crystal Output. These pins are
provided for the connection of an external 14.318
MHz crystal to provide the reference clock for the
internal frequency synthesizer, from which the
HCLK and CLK24M signals are generated.
PCI_CLKI
33 MHz PCI Input Clock. This signal
must be connected to a clock generator and is
usually connected to PCI_CLKO.
PCI_CLKO 33 MHz PCI Output Clock. This is the
master PCI bus clock output.
ISA_CLK ISA Clock Output (also Multiplexer
Select Line For IPC). This pin produces the Clock
signal for the ISA bus. It is also used with
ISA_CLK2X as the multiplexer control lines for the
Interrupt Controller Interrupt input lines. This is a
divided down version of the PCICLK or OSC14M.
ISA_CLKX2
ISA Clock Output (also Multiplexer
Select Line For IPC). This pin produces a signal at
twice the frequency of the ISA bus Clock signal. It
is also used with ISA_CLK as the multiplexer
control lines for the Interrupt Controller Interrupt
input lines.
CLK14M
ISA bus synchronisation clock. This is
the buffered 14.318 MHz clock to the ISA bus.
HCLK Host Clock. This is the host clock. Its
frequency can vary from 25 to 66 MHz. All host
transactions
and
PCI
transactions
are
synchronized to this clock. Host transactions
executed by the DRAM controller are also driven
by this clock.
DEV_CLK
24 MHz Peripheral Clock (floppy
drive). This 24 MHz signal is provided as a
convenience for the system integration of a Floppy
Disk driver function in an external chip. This clock
signal is not available in Local Bus mode.
DCLK 135 MHz Dot Clock. This is the dot clock,
which drives graphics display cycles. Its frequency
can be as high as 135 MHz, and it is required to
have a worst case duty cycle of 60-40. For further
details, refer to Section 3.1.4. bit 4.
2.2.2. MEMORY INTERFACE
MCLKI Memory Clock Input. This clock is driving
the SDRAM controller, the graphics engine and
display controller. This input should be a buffered
version of the MCLKO signal with the track lengths
between the buffer and the pin matched with the
track lengths between the buffer and the Memory
Banks.
MCLKO
Memory Clock Output. This clock drives
the Memory Banks on board and is generated
from an internal PLL.
The STPC Atlas MClock signal can run up to
100MHz reliably, but PCB layout is so critical that
the maximum guaranteed speed is 90MHz
CS#[1:0]
Chip Select These signals are used to
disable or enable device operation by masking or
enabling all SDRAM inputs except MCLK, CKE,
and DQM.
CS#[2]/MA[11] Chip Select/Bank Address This
pin is CS#[2] in the case when 16-Mbit devices are
used. For all other densities, it becomes MA[11].
CS#[3]/MA[12]/BA[1]
Chip
Select/
Memory
Address/ Bank Address This pin is CS#[3] in the
case when 16 Mbit devices are used. For all other
densities, it becomes MA[12] when 2 internal
banks devices are used and BA[1] when 4 internal
bank devices are used.
MA[10:0]
Memory Address. Multiplexed row and
column address lines.
BA[0] Bank Address. Internal bank address line.
MD[63:0] Memory Data. This is the 64-bit memory
data bus. This bus is also used as input at the
rising edge of SYSRSTI# to latch in power-up
configuration information into the ADPC strap
registers.
RAS#[1:0]
Row Address Strobe. There are two
active-low row address strobe output signals. The
RAS# signals drive the memory devices directly
without any external buffering.


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