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STPCI2GDY Datasheet(PDF) 15 Page - STMicroelectronics

Part No. STPCI2GDY
Description  X86 Core PC Compatible System-on-Chip for Terminals
Download  111 Pages
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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STPCI2GDY Datasheet(HTML) 15 Page - STMicroelectronics

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PIN DESCRIPTION
Issue 1.0 - July 24, 2002
15/111
ISA BUS INTERFACE
LA[23:17]
O BD8STRUP_FT
Unlatched Address Bus
7
SA[19:0]
O BD8STRUP_FT
Latched Address Bus
20
SD[15:0]
I/O BD8STRP_FT
Data Bus
16
IOCHRDY
I
BD8STRUP_FT
I/O Channel Ready
1
ALE
O BD4STRP_FT
Address Latch Enable
1
BHE#
O BD8STRUP_FT
System Bus High Enable
1
MEMR#, MEMW#
I/O BD8STRUP_FT
Memory Read & Write
2
SMEMR#, SMEMW#
O BD8STRP_FT
System Memory Read and Write
2
IOR#, IOW#
I/O BD8STRUP_FT
I/O Read and Write
2
MASTER#
I
BD4STRUP_FT
Add On Card Owns Bus
1
MCS16#
I
BD4STRUP_FT
Memory Chip Select 16
1
IOCS16#
I
BD4STRUP_FT
I/O Chip Select 16
1
REF#
I
BD8STRP_FT
Refresh Cycle
1
AEN
O BD8STRUP_FT
Address Enable
1
IOCHCK#
I
BD4STRUP_FT
I/O Channel Check (ISA)
1
RTCRW#
O BD4STRP_FT
RTC Read / Write#
1
RTCDS#
O BD4STRP_FT
RTC Data Strobe
1
RTCAS
O BD4STRP_FT
RTC Address Strobe
1
RMRTCCS#
O BD4STRP_FT
ROM / RTC Chip Select
1
GPIOCS#
I/O BD4STRP_FT
General Purpose Chip Select
1
IRQ_MUX[3:0]
I
BD4STRP_FT
Multiplexed Interrupt Request
4
DACK_ENC[2:0]
O BD4STRP_FT
DMA Acknowledge
3
DREQ_MUX[1:0]
I
BD4STRP_FT
Multiplexed DMA Request
2
TC
O BD4STRP_FT
ISA Terminal Count
1
ISAOE#
I
BD4STRP_FT
ISA (0) / IDE (1) SELECTION
1
KBCS#
I/O BD4STRP_FT
External Keyboard CHIP SELECT
1
ZWS#
I
BD4STRP_FT
ZERO WAIT STATE
1
PCMCIA INTERFACE
RESET
O BD8STRP_FT
Reset
1
A[23:0]
O BD8STRUP_FT
Address Bus
24
D[15:0]
I/O BD8STRP_FT
Data Bus
16
IORD#, IOWR#
O BD8STRUP_FT
I/O Read and Write
2
WP / IOIS16#
I
BD4STRUP_FT
DMA Request // Write Protect
I/O Size is 16 bit
1
BVD2, BVD1
I
BD4STRUP_FT
Battery Voltage Detect
2
READY# / IREQ#
I
BD4STRUP_FT
Busy / Ready# // Interrupt Request
1
WAIT#
I
BD8STRUP_FT
Wait
1
OE#
O BD8STRUP_FT
Output Enable // DMA Terminal Count
1
WE#
O BD4STRP_FT
Write Enable // DMA Terminal Count
1
REG#
O BD4STRUP_FT
DMA Acknowledge // Register
1
CD2#, CD1#
I
BD4STRUP_FT
Card Detect
2
CE2#, CE1#
O BD4STRP_FT
Card Enable
2
VCC5_EN
O BD4STRP_FT
Power Switch control: 5 V power
1
VCC3_EN
O BD8STRP_FT
Power Switch control: 3.3 V power
1
VPP_PGM
O BD8STRP_FT
Power Switch control: Program power
1
VPP_VCC
O BD4STRP_FT
Power Switch control: VCC power
1
GPI#
I
BD4STRP_FT
General Purpose Input
1
Table 2-2. Definition of Signal Pins
Signal Name
Dir
Buffer Type1
Description
Qty
Note1; See Table 2-3 for buffer type descriptions


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