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STPCI2GDY Datasheet(PDF) 99 Page - STMicroelectronics

Part No. STPCI2GDY
Description  X86 Core PC Compatible System-on-Chip for Terminals
Download  111 Pages
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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STPCI2GDY Datasheet(HTML) 99 Page - STMicroelectronics

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DESIGN GUIDELINES
Issue 1.0 - July 24, 2002
99/111
6.4.4.3. Board Layout Issues
The physical layout of the motherboard PCB
assumed in this presentation is as shown in Figure
6-29. For the PCI interface, the most critical signal
is the clock. Any skew between the clocks at the
PCI components and the STPC will impact the
timing budget. In order to get well matched clocks
at all components it is recommended that all the
PCI clocks are individually driven from a serial
resistance with matched routing lengths. In other
words, all clock line lengths that go from the
resistor to the PCI chips (PCICLKx) must be
identical.
The figure below is for PCI devices soldered on-
board. In the case of a PCI slot, the wire length
must be shortened by 2.5" to compensate the
clock layout on the PCI board. The maximum
clock skew between all devices is 2ns according
to PCI specifications.
The Figure 6-30 describes a typical clock delay
implementation. The exact timing constraints are
listed in the PCI section of the Electrical
Specifications Chapter.
Figure 6-29. Typical PCI clock routing
Length(PCICLKI) = Length(PCICLKx) with x = {A,B,C}
Note: The value of 22 Ohms corresponds to tracks with Z0 = 70 Ohms.
PCICLKI
PCICLKO
PCICLKA
PCICLKB
PCICLKC
Device A
Device B
Device C
Figure 6-30. Clocks relationships
PCICLKO
PCICLKI
HCLK
PCICLKx


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