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STPCI2GDY Datasheet(PDF) 95 Page - STMicroelectronics

Part No. STPCI2GDY
Description  X86 Core PC Compatible System-on-Chip for Terminals
Download  111 Pages
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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STPCI2GDY Datasheet(HTML) 95 Page - STMicroelectronics

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DESIGN GUIDELINES
Issue 1.0 - July 24, 2002
95/111
The maximum skew between pins for this part is
250ps. The important factors for the clock buffer
are a consistent drive strength and low skew
between the outputs. The delay through the buffer
is not important so it does not have to be a zero
delay PLL type buffer. The trace lengths from the
clock driver to the DIMM CKn pins should be
matched exactly. Since the propagation speed
can vary between PCB layers, the clocks should
be routed in a consistent way. The routing to the
STPC memory input should be longer by 75 mm to
compensate for the extra clock routing on the
DIMM. Also a 20 pF capacitor should be placed as
near as possible to the clock input of the STPC to
compensate for the DIMM’s higher clock load. The
impedance of the trace used for the clock routing
should be matched to the DIMM clock trace
impedance (60-75 ohms)
.To minimise crosstalk
the clocks should be routed with spacing to
adjacent tracks of at least twice the clock trace
width. For designs which use SDRAMs directly
mounted on the motherboard PCB all the clock
trace lengths should be matched exactly.
The DIMM sockets should be populated starting
with the furthest DIMM from the STPC device first
(DIMM1). There are two types of DIMM devices;
single-row and dual-row. The dual-row devices
require two chip select signals to select between
the two rows. A STPC device with 4 chip select
control lines could control either 4 single-row
DIMMs or 2 dual-row DIMMs. When only 2 chip
select control lines are activated, only two single-
row DIMMs or one dual-row DIMM can be
controlled.
6.4.3.4. Summary
For unbuffered DIMMs the address/control signals
will be the most critical for timing. The simulations
show that for these signals the best way to drive
them is to use a parallel termination. For
applications where speed is not so critical series
termination can be used as this will save power.
Using a low impedance such as 50
Ω for these
critical traces is recommended as it both reduces
the delay and the overshoot.
The other memory interface signals will typically
be not as critical as the address/control signals.
Using lower impedance traces is also beneficial
for the other signals but if their timing is not as
critical as the address/control signals they could
use the default value. Using a lower impedance
implies using wider traces which may have an
impact on the routing of the board.
The layout of this interface can be validated by an
electrical
simulation
using
the
IBIS
model
available on the STPC web site.
6.4.3.5. Clock topology for on-board SDRAM
Figure 6-24 and Figure 6-25 give the recommend-
ed clock topology and the resulting IBIS simulation
in the case of four on-board SDRAM devices and
no clock buffer.
6.4.3.6. Clock topology for standard DIMM
Figure 6-26 and Figure 6-27 give the recommend-
ed clock topology and the resulting IBIS simulation
in the case of a standard DIMM with the use of a
clock buffer.
Figure 6-24. Recommended topology for 4 on-board SDRAMs (IBIS model)
MCLKI
MCLKO
18 Ohms
400 mils
3500 mils
3500 mils
3500 mils
3500 mils
400 mils
MCLK0
MCLK1
MCLK2
MCLK3
Track impedance= 75 Ohms
Trace thickness = 0.72 mil
Trace width = 4 to 8 mils


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