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STPCCONSUMER-II Datasheet(PDF) 3 Page - STMicroelectronics

Part No. STPCCONSUMER-II
Description  X86 Core PC Compatible Information Appliance System-on-Chip
Download  93 Pages
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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STPCCONSUMER-II Datasheet(HTML) 3 Page - STMicroelectronics

 
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STPC
® CONSUMER-II
Release 1.5 - January 29, 2002
3/93
s
PCI Controller
s
Fully compliant with PCI 2.1 specification.
s
Integrated PCI arbitration interface. Up to 3
masters can connect directly. External PAL
allows for greater than 3 masters.
s
Translation of PCI cycles to ISA bus.
s
Translation of ISA master initiated cycle to
PCI.
s
Support for burst read/write from PCI master.
s
PCI clock is 1/2, 1/3 or 1/4 cpu bus clock.
s
ISA master/slave
s
Generates the ISA clock from either
14.318 MHz oscillator clock or PCI clock
s
Supports programmable extra wait state for
ISA cycles
s
Supports I/O recovery time for back to back
I/O cycles.
s
Fast Gate A20 and Fast reset.
s
Supports the single ROM that C, D, or E.
blocks shares with F block BIOS ROM.
s
Supports flash ROM.
s
Supports ISA hidden refresh.
s
Buffered DMA & ISA master cycles to reduce
bandwidth utilization of the PCI and Host
bus.
s
Local Bus interface
s
Multiplexed with ISA/DMA interface.
s
Low latency asynchronous bus
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22-bit address bus.
s
16-bit data bus with word steering capability.
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Programmable timing (Host clock granularity)
s
Two Programmable Flash Chip Select.
s
Four Programmable I/O Chip Select.
s
Supports 32-bit Flash burst.
s
Two-level hardware key protection for Flash
boot block protection.
s
Supports two banks of 16 MB flash devices
with boot block shadowed to 0x000F0000.
s
IDE Interface
s
Supports PIO
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Transfer Rates to 22 MBytes/sec
s
Supports up to 4 IDE devices
s
Concurrent channel operation (PIO modes) -
4 x 32-Bit Buffer FIFOs per channel
s
Support for PIO mode 3 & 4.
s
Individual drive timing for all four IDE devices
s
Supports both legacy & native IDE modes
s
Supports hard drives larger than 528MB
s
Support for CD-ROM and tape peripherals
s
Backward compatibility with IDE (ATA-1).
s
Drivers for Windows and other Operating
Systems
s
Integrated Peripheral Controller
s
2X8237/AT compatible 7-channel DMA
controller.
s
2X8259/AT compatible interrupt Controller.
16 interrupt inputs - ISA and PCI.
s
Three 8254 compatible Timer/Counters.
s
Co-processor error support logic.
s
Power Management
s
Four power saving modes: On, Doze,
Standby, Suspend.
s
Programmable system activity detector
s
Supports Intel & Cyrix SMM and APM.
s
Supports STOPCLK.
s
Supports IO trap & restart.
s
Independent peripheral time-out timer to
monitor hard disk, serial & parallel port.
s
128K SM_RAM address space from
0xA0000 to 0xB0000
s
JTAG
s
Boundary Scan compatible IEEE1149.1.
s
Scan Chain control.
s
Bypass register compatible IEEE1149.1.
s
ID register compatible IEEE1149.1.
s
RAM BIST control.
The STPC Consumer-II has undergone an errata fix upgrade. The different versions can be differenciated by the part
number. Both versions are pin to pin compatible and there are some software extensions that have been added to the
upgraded parts. The parts labeled STPCC5 are the upgraded parts and the differences are identified in both the Datash-
eet and Programming Manual. All parts labeled STPCC4 do not support the new features outlined in the documentation.
Where nor C4 nor C5 are specified, the information or feature applies to both versions.


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