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STPCCLIENT Datasheet(PDF) 5 Page - STMicroelectronics

Part No. STPCCLIENT
Description  PC Compatible Embedded Microprocessor
Download  48 Pages
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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STPCCLIENT Datasheet(HTML) 5 Page - STMicroelectronics

 
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UPDATE HISTORY FOR OVERVIEW
Issue 1.7 - February 8, 2000
5/48
UPDATE HISTORY FOR OVERVIEW
The following changes have been made to the Board Layout Chapter on 02/02/2000.
The following changes have been made to the Board Layout Chapter from Revision 1.0 to Release 1.2.
Section
Change
Text
Added
To check if your memory device is supported by the STPC, please refer to
Table 7-69 Host Address to MA Bus Mappingin the Programming Manual.
Section
Change
Text
N/A
Replaced
“fully PC compatible” With “with DOS, Windows and UNIX compatibility”
N/A
Replaced
“133 MHz” With 75 MHz”
N/A
Removed
“Drivers for Windows and other operating systems.”
N/A
Removed
Requires external frequency synthesizer and reference sources.”
N/A
Replaced
Chroma and colour keying for integrated video overlay.” With “Chroma and colour
keying
allowing video overlay.
N/A
Replaced
“Accepts video inputs in CCIR 601/656 or ITU-R 601/656, and decodes the
stream.” With “Decodes video inputs in ITU-R 601/656 compatible formats.
N/A
Replaced
“Fully compliant with PCI 2.1 specification.
Integrated PCI arbitration interface. Up to 3 masters can connect directly.
External PAL allows for greater than 3 masters.”
With
“Integrated PCI arbitration interface able to directly manage up to 3 PCI
masters at a time.”
N/A
Replaced
“0.33X and 0.5X CPU clock PCI clock.” With “The PCI clock runs at a third or
half CPU clock speed.”
N/A
Removed
“Supports flash ROM.”
N/A
Replaced
“Supports ISA hidden refresh.” With “Supports flash ROM.”
N/A
Replaced
Buffered DMA & ISA master cycles to reduce bandwidth utilization of the PCI
and Host bus. NSP compliant.” With “Buffered DMA & ISA master cycles to
reduce bandwidth utilization of the PCI and Host bus. “
N/A
Replaced
Supports PIO and Bus Master IDE” With “Supports PIO”
N/A
Removed
“Transfer Rates to 22 MBytes/sec”
N/A
Added
“Individual drive timing for all four IDE devices “
N/A
Replaced
“Concurrent channel operation (PIO & DMA modes) - 4 x 32-Bit Buffer FIFO
per channel”
With
“Concurrent channel operation (PIO modes) - 4 x 32-Bit Buffer FIFO per
channel”
N/A
Removed
“Support for DMA mode 1 & 2.”
“Support for 11.1/16.6 MB/s, I/O Channel Ready PIO data transfers.”
“Supports 13.3/16.6 MB/s DMA data transfers”
“Bus Master with scatter/gather capability “
“Multi-word DMA support for fast IDE drives “
“Individual drive timing for all four IDE devices “
“Supports both legacy & native IDE modes”
“Supports hard drives larger than 528MB”
“Support for CD-ROM and tape peripherals”
“Backward compatibility with IDE (ATA-1).”
“Drivers for Windows and other OSes”


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