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STPCCLIENT Datasheet(PDF) 1 Page - STMicroelectronics

Part No. STPCCLIENT
Description  PC Compatible Embedded Microprocessor
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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STPCCLIENT Datasheet(HTML) 1 Page - STMicroelectronics

 
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Issue 1.7
1/48
®
STPC CLIENT
PC Compatible Embedded Microprocessor
February 8, 2000
Figure 1. Logic Diagram
POWERFUL X86 PROCESSOR
64-BIT 66MHz BUS INTERFACE
64-BIT DRAM CONTROLLER
SVGA GRAPHICS CONTROLLER
UMA ARCHITECTURE
VIDEO SCALER
VIDEO OUTPUT PORT
VIDEO INPUT PORT
CRT CONTROLLER
135MHz RAMDAC
2 OR 3 LINE FLICKER FILTER
SCAN CONVERTER
PCI MASTER / SLAVE / ARBITER
ISA MASTER/SLAVE
IDE CONTROLLER
DMA CONTROLLER
INTERRUPT CONTROLLER
TIMER / COUNTERS
POWER MANAGEMENT
STPC CLIENT OVERVIEW
The STPC Client integrates a standard 5th
generation x86 core, a DRAM controller, a
graphics
subsystem, a
video
pipeline,
and
support
logic including PCI, ISA, and IDE
controllers
to
provide
a
single
Consumer
orientated PC compatible subsystem on a single
device.
The device is based on a tightly coupled Unified
Memory Architecture (UMA), sharing the same
memory array between the CPU main memory
and the graphics and video frame buffers.
Extra facilities are implemented to handle video
streams. Features include smooth scaling and
colour space conversion of the video input stream
and mixing of the video stream with non-video
data from the frame buffer. The chip also includes
anti-flicker filters to provide a stable, high-quality
Digital TV output.
The STPC Client is packaged in a 388 Plastic Ball
Grid Array (PBGA).
PBGA388
x86
Core
Host I/F
DRAM
VIP
PCI
PCI BUS
ISA
EID
PCI
ISA BUS
CRT
HW
Monitor
TV Output
SYNC Output
Col-
Col-
our
Vid-
CCIR Input
EIDE
2D
Anti-
IPC


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