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FDMF6704A Rev. C

Module Power Loss and Efficiency

Measurement and Calculation

Refer to Figure 22 for module power loss testing method. Power

loss calculation are as follows:

PCB Layout Guideline

Figure 23 shows a proper layout example of FDMF6704A and

stable current flow, heat radiation and system performance.

Following is a guideline which the PCB designer should

consider:

of FDMF6704A to help reduce input current ripple component

induced by switching operation.

2. It is critical that the VSWH copper has minimum area for

lower switching noise emission. VSWH copper trace should

also be wide enough for high current flow. Other signal routing

path, such as PWM IN and BOOT signal, should be considered

with care to avoid noise pickup from VSWH copper area.

3. Output inductor location should be as close as possible to the

FDMF6704A for lower power loss due to copper trace.

very effective at minimizing ringing. In most cases, no snubber

will be required. If a snubber is used, it should be placed near

the FDMF6704A. The resistor and capacitor need to be of

proper size for power dissipation.

5. Place ceramic bypass capacitor and boot capacitor as close

power. Routing width and length should also be considered.

6. Ringing at the Boot pin is most effectively controlled by close

placement of the capacitor. Do not add an additional Boot to

PGND capacitor. This may lead to excess current flow through

the Boot diode.

7. Use multiple Vias on each copper area to interconnect each

top, inner and bottom layer to help smooth current flow and heat

conduction. Vias should be relatively large and of reasonable

inductance.

Figure 22. Power Loss Measurement Block Diagram

Figure 23. Typical PCB Layout Example (Top View)

DISB#

PWM

CGND PGND

BOOT

VSWH

DISB#

PWM Input

VDRV

SMOD#

PHASE

A

A

A

V

SMOD#