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FDMF6704A Datasheet(PDF) 10 Page - Fairchild Semiconductor |
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FDMF6704A Datasheet(HTML) 10 Page - Fairchild Semiconductor |
10 / 12 page 10 www.fairchildsemi.com FDMF6704A Rev. C Module Power Loss and Efficiency Measurement and Calculation Refer to Figure 22 for module power loss testing method. Power loss calculation are as follows: (a) PIN = (VIN x IIN) + (V5V x I5V) (W) (b) POUT = VO x IOUT (W) (c) PLOSS = PIN - POUT (W) (d) Efficiency = 100 x POUT/PIN (%) PCB Layout Guideline Figure 23 shows a proper layout example of FDMF6704A and critical parts. All of high current flow path, such as VIN, VSWH, VOUT and GND copper, should be short and wide for better and stable current flow, heat radiation and system performance. Following is a guideline which the PCB designer should consider: 1. Input bypass capacitors should be close to VIN and PGND pin of FDMF6704A to help reduce input current ripple component induced by switching operation. 2. It is critical that the VSWH copper has minimum area for lower switching noise emission. VSWH copper trace should also be wide enough for high current flow. Other signal routing path, such as PWM IN and BOOT signal, should be considered with care to avoid noise pickup from VSWH copper area. 3. Output inductor location should be as close as possible to the FDMF6704A for lower power loss due to copper trace. 4. The PowerTrench® 5 MOSFETs used in the output stage are very effective at minimizing ringing. In most cases, no snubber will be required. If a snubber is used, it should be placed near the FDMF6704A. The resistor and capacitor need to be of proper size for power dissipation. 5. Place ceramic bypass capacitor and boot capacitor as close to VCIN and BOOT pin of FDMF6704A in order to supply stable power. Routing width and length should also be considered. 6. Ringing at the Boot pin is most effectively controlled by close placement of the capacitor. Do not add an additional Boot to PGND capacitor. This may lead to excess current flow through the Boot diode. 7. Use multiple Vias on each copper area to interconnect each top, inner and bottom layer to help smooth current flow and heat conduction. Vias should be relatively large and of reasonable inductance. Figure 22. Power Loss Measurement Block Diagram Figure 23. Typical PCB Layout Example (Top View) DISB# PWM CGND PGND VCIN VIN BOOT VSWH DISB# PWM Input CVIN CBOOT COUT V5V CVDRV VDRV CVCIN SMOD# PHASE A I5V A VIN IIN A VOUT IOUT V VO SMOD# |
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