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TUSB6015IZQE Datasheet(PDF) 9 Page - Texas Instruments |
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TUSB6015IZQE Datasheet(HTML) 9 Page - Texas Instruments |
9 / 28 page TUSB6015ZQE SLLS937 REVISION 1.4 SEPTEMBER 10, 2008 Power Sequencing Guidelines Power-On Reset The system reset function ensures an orderly start-up sequence for the TUSB6015. There is a one active low external system reset input (RSTn). The reset initializes the Power/Reset/Clock Manager (PRCM) module, which in turn generates all the internal resets to initialize USB 2.0 PHY Macro and synchronous logic in the core. While reset is asserted (active low), the dual functional pin is sampled to determine device configuration after reset. Since TUSB6015 relies on a dual function pin to configure the device during reset, the reset must be sufficiently long for (external) marginal pull-up/pull-down to achieve the intended levels. Reset pulse duration should be at least three times actual RC constant time (with typical 22 kOhm marginal pull-up resistor with 50 pF load, reset pulse should be at least 3.3 µs). All functional pins remain in same state even after RSTn is de-asserted and stay in that state until internal core reset is cleared. The internal core reset is held for 16 system clock cycles following low-to-high RSTn transition. Upon power-on reset, the following must be determined for proper device initialization: System reference clock source Device uses dual-mode pin to determine initial clock input setup. Dual function pin is latched during the reset. After the reset this terminal assumes the normal functionality. External Pin Function Description GPIO6 Reference Clock Frequency Select Determines the reference clock pin 0 – 38.4 MHz (CLKIN_38_4 pin is used) 1 – 19.2 MHz (CLKIN_19_2_24 pin is used) CLK_24_SEL CLKIN_19_2_24 Frequency Select Determines the reference frequency of the CLKIN_19_2_24 pin 0 – RSVD 1 – 19.2 MHz If GPIO6 is low at reset, this pin will have no effect on clock selection. Upon exiting reset, the USB 2.0 PHY is not in the suspend state and the system clock (60 MHz) is enabled and free running. The USB 2.0 HS Peripheral Controller Core powers up and a session is not enabled. With session not enabled, all the USB 2.0 HS Peripheral Controller Core State Machine’s are in the idle state. After reset is de-asserted, the device asserts the DevReady interrupt to the External Host to indicate that it is ready to be programmed. The host reads the NOR Flash Interrupt Source register and decides how to proceed based on the device’s current status. 9 WWW.TI.COM |
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