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LCMXO1200LUTSC-3T144C Datasheet(PDF) 24 Page - Lattice Semiconductor |
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LCMXO1200LUTSC-3T144C Datasheet(HTML) 24 Page - Lattice Semiconductor |
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24 / 95 page  2-21 Architecture Lattice Semiconductor MachXO Family Data Sheet the system. These capabilities make the MachXO ideal for many multiple power supply and hot-swap applica- tions. Sleep Mode The MachXO “C” devices (VCC = 1.8/2.5/3.3V) have a sleep mode that allows standby current to be reduced dra- matically during periods of system inactivity. Entry and exit to Sleep mode is controlled by the SLEEPN pin. During Sleep mode, the logic is non-operational, registers and EBR contents are not maintained, and I/Os are tri- stated. Do not enter Sleep mode during device programming or configuration operation. In Sleep mode, power sup- plies are in their normal operating range, eliminating the need for external switching of power supplies. Table 2-11 compares the characteristics of Normal, Off and Sleep modes. Table 2-11. Characteristics of Normal, Off and Sleep Modes SLEEPN Pin Characteristics The SLEEPN pin behaves as an LVCMOS input with the voltage standard appropriate to the VCC supply for the device. This pin also has a weak pull-up, along with a Schmidt trigger and glitch filter to prevent false triggering. An external pull-up to VCC is recommended when Sleep Mode is not used to ensure the device stays in normal oper- ation mode. Typically, the device enters sleep mode several hundred nanoseconds after SLEEPN is held at a valid low and restarts normal operation as specified in the Sleep Mode Timing table. The AC and DC specifications por- tion of this data sheet shows a detailed timing diagram. Oscillator Every MachXO device has an internal CMOS oscillator. The oscillator can be routed as an input clock to the clock tree or to general routing resources. The oscillator frequency can be divided by internal logic. There is a dedicated programming bit to enable/disable the oscillator. The oscillator frequency ranges from 18MHz to 26MHz. Configuration and Testing The following section describes the configuration and testing features of the MachXO family of devices. IEEE 1149.1-Compliant Boundary Scan Testability All MachXO devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port shares its power supply with one of the VCCIO Banks (MachXO256: VCCIO1; MachXO640: VCCIO2; MachXO1200 and MachXO2280: VCCIO5) and can operate with LVCMOS3.3, 2.5, 1.8, 1.5, and 1.2 standards. For more details on boundary scan test, please see information regarding additional technical documentation at the end of this data sheet. Characteristic Normal Off Sleep SLEEPN Pin High — Low Static Icc Typical <10mA 0 Typical <100uA I/O Leakage <10µA <1mA <10µA Power Supplies VCC/VCCIO/VCCAUX Normal Range 0 Normal Range Logic Operation User Defined Non Operational Non operational I/O Operation User Defined Tri-state Tri-state JTAG and Programming circuitry Operational Non-operational Non-operational EBR Contents and Registers Maintained Non-maintained Non-maintained |
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Similar Description - LCMXO1200LUTSC-3T144C |
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