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LCMXO1200LUTSC-3T100C Datasheet(PDF) 43 Page - Lattice Semiconductor |
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LCMXO1200LUTSC-3T100C Datasheet(HTML) 43 Page - Lattice Semiconductor |
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43 / 95 page  3-17 DC and Switching Characteristics Lattice Semiconductor MachXO Family Data Sheet Flash Download Time JTAG Port Timing Specifications Figure 3-5. JTAG Port Timing Waveforms Symbol Parameter Min. Typ. Max. Units tREFRESH Minimum VCC or VCCAUX (later of the two supplies) to Device I/O Active LCMXO256 — — 0.4 ms LCMXO640 — — 0.6 ms LCMXO1200 — — 0.8 ms LCMXO2280 — — 1.0 ms Symbol Parameter Min. Max. Units fMAX TCK [BSCAN] clock frequency — 25 MHz tBTCP TCK [BSCAN] clock pulse width 40 — ns tBTCPH TCK [BSCAN] clock pulse width high 20 — ns tBTCPL TCK [BSCAN] clock pulse width low 20 — ns tBTS TCK [BSCAN] setup time 8 — ns tBTH TCK [BSCAN] hold time 10 — ns tBTRF TCK [BSCAN] rise/fall time 50 — mV/ns tBTCO TAP controller falling edge of clock to output valid — 10 ns tBTCODIS TAP controller falling edge of clock to output disabled — 10 ns tBTCOEN TAP controller falling edge of clock to output enabled — 10 ns tBTCRS BSCAN test capture register setup time 8 — ns tBTCRH BSCAN test capture register hold time 25 — ns tBUTCO BSCAN test update register, falling edge of clock to output valid — 25 ns tBTUODIS BSCAN test update register, falling edge of clock to output disabled — 25 ns tBTUPOEN BSCAN test update register, falling edge of clock to output enabled — 25 ns Rev. A 0.19 TMS TDI TCK TDO Data to be captured from I/O Data to be driven out to I/O a t a D d il a V a t a D d il a V a t a D d il a V a t a D d il a V Data Captured tBTCPH tBTCPL tBTCOEN tBTCRS tBTUPOEN tBUTCO tBTUODIS tBTCRH tBTCO tBTCODIS tBTS tBTH tBTCP |
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