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LFEC3E-3TN100I Datasheet(PDF) 2 Page - Lattice Semiconductor |
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LFEC3E-3TN100I Datasheet(HTML) 2 Page - Lattice Semiconductor |
2 / 163 page www.latticesemi.com 1-1 Introduction_01.3 May 2005 Data Sheet © 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Features ■ Extensive Density and Package Options • 1.5K to 32.8K LUT4s • 65 to 496 I/Os • Density migration supported ■ sysDSP™ Block (LatticeECP™ Versions) • High performance multiply and accumulate • 4 to 8 blocks − 4 to 8 36x36 multipliers or – 16 to 32 18x18 multipliers or − 32 to 64 9x9 multipliers ■ Embedded and Distributed Memory • 18 Kbits to 498 Kbits sysMEM™ Embedded Block RAM (EBR) • Up to 131 Kbits distributed RAM • Flexible memory resources: − Distributed and block memory ■ Flexible I/O Buffer • Programmable sysI/O™ buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL − SSTL 3/2 Class I, II, SSTL18 Class I − HSTL 18 Class I, II, III, HSTL15 Class I, III − PCI − LVDS, Bus-LVDS, LVPECL, RSDS ■ Dedicated DDR Memory Support • Implements interface up to DDR400 (200MHz) ■ sysCLOCK™ PLLs • Up to four analog PLLs per device • Clock multiply, divide and phase shifting ■ System Level Support • IEEE Standard 1149.1 Boundary Scan, plus ispTRACY™ internal logic analyzer capability • SPI boot flash interface • 1.2V power supply ■ Low Cost FPGA • Features optimized for mainstream applications • Low cost TQFP and PQFP packaging Table 1-1. LatticeECP/EC Family Selection Guide Device LFEC1 LFEC3 LFEC6/ LFECP6 LFEC10/ LFECP10 LFEC15/ LFECP15 LFEC20/ LFECP20 LFEC33/ LFECP33 PFU/PFF Rows 12 16 24 32 40 44 64 PFU/PFF Columns 16 24 32 40 48 56 64 PFUs/PFFs 192 384 768 1280 1920 2464 4096 LUTs (K) 1.5 3.1 6.1 10.2 15.4 19.7 32.8 Distributed RAM (Kbits) 6 12 25 41 61 79 131 EBR SRAM (Kbits) 18 55 92 276 350 424 498 EBR SRAM Blocks 2 6 10 30 38 46 54 sysDSP Blocks 1 — — 45678 18x18 Multipliers 1 — — 16 20 24 28 32 VCC Voltage (V) 1.2 1.2 1.2 1.2 1.2 1.2 1.2 Number of PLLs 2224444 Packages and I/O Combinations: 100-pin TQFP (14 x 14 mm) 67 67 144-pin TQFP (20 x 20 mm) 97 97 97 208-pin PQFP (28 x 28 mm) 112 145 147 147 256-ball fpBGA (17 x 17 mm) 160 195 195 195 484-ball fpBGA (23 x 23 mm) 224 288 352 360 360 672-ball fpBGA (27 x 27 mm) 400 496 1. LatticeECP devices only. LatticeECP/EC Family Data Sheet Introduction |
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