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V62C51864 Datasheet(PDF) 8 Page - Mosel Vitelic, Corp |
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V62C51864 Datasheet(HTML) 8 Page - Mosel Vitelic, Corp |
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8 / 10 page  8 V62C51864 Rev. 2.1 June 1998 MOSEL VITELIC V62C51864 Switching Waveforms (Write Cycle) Write Cycle 1 (WE Controlled)(4) Write Cycle 2 (CE Controlled)(4) NOTES: 1. The internal write time of the memory is defined by the overlap of CE 1 and CE2 active and WElow. Both signals must be active to initiate and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 2. tWR is measured from the earlier of CE 1 or WE going HIGH, or CE2 going LOW at the end of the write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 4. OE = VIL or VIH. However it is recommended to keep OE at VIH during write cycle to avoid bus contention. 5. If CE1 is LOW and CE2 is HIGH during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 6. tCW is measured from CE1 going LOW or CE2 going HIGH to the end of write. ADDRESS OUTPUT INPUT CE1 CE2 WE 51864 12 tWC tCW (6) tCW (6) tDW tDH tAW tWR (2) tWHZ tWP (1) tAS ADDRESS OUTPUT High-Z INPUT CE1 CE2 WE 51864 13 tWC tDW tDH tAW tCW (6) tCW (6) tWR (2) tAS (4) (5) |
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Similar Description - V62C51864 |
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