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LM3S600-IRN25-A1T Datasheet(PDF) 3 Page - Bookham, Inc. |
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LM3S600-IRN25-A1T Datasheet(HTML) 3 Page - Bookham, Inc. |
3 / 378 page Table of Contents About This Document .................................................................................................................... 15 Audience .............................................................................................................................................. 15 About This Manual ................................................................................................................................ 15 Related Documents ............................................................................................................................... 15 Documentation Conventions .................................................................................................................. 15 1 Architectural Overview ...................................................................................................... 17 1.1 Product Features ...................................................................................................................... 17 1.2 Target Applications .................................................................................................................... 21 1.3 High-Level Block Diagram ......................................................................................................... 21 1.4 Functional Overview .................................................................................................................. 22 1.4.1 ARM Cortex™-M3 ..................................................................................................................... 23 1.4.2 Motor Control Peripherals .......................................................................................................... 23 1.4.3 Analog Peripherals .................................................................................................................... 24 1.4.4 Serial Communications Peripherals ............................................................................................ 24 1.4.5 System Peripherals ................................................................................................................... 25 1.4.6 Memory Peripherals .................................................................................................................. 26 1.4.7 Additional Features ................................................................................................................... 27 1.4.8 Hardware Details ...................................................................................................................... 27 2 ARM Cortex-M3 Processor Core ...................................................................................... 28 2.1 Block Diagram .......................................................................................................................... 29 2.2 Functional Description ............................................................................................................... 29 2.2.1 Serial Wire and JTAG Debug ..................................................................................................... 29 2.2.2 Embedded Trace Macrocell (ETM) ............................................................................................. 30 2.2.3 Trace Port Interface Unit (TPIU) ................................................................................................. 30 2.2.4 ROM Table ............................................................................................................................... 30 2.2.5 Memory Protection Unit (MPU) ................................................................................................... 30 2.2.6 Nested Vectored Interrupt Controller (NVIC) ................................................................................ 30 3 Memory Map ....................................................................................................................... 34 4 Interrupts ............................................................................................................................ 36 5 JTAG Interface .................................................................................................................... 38 5.1 Block Diagram .......................................................................................................................... 39 5.2 Functional Description ............................................................................................................... 39 5.2.1 JTAG Interface Pins .................................................................................................................. 40 5.2.2 JTAG TAP Controller ................................................................................................................. 41 5.2.3 Shift Registers .......................................................................................................................... 42 5.2.4 Operational Considerations ........................................................................................................ 42 5.3 Initialization and Configuration ................................................................................................... 43 5.4 Register Descriptions ................................................................................................................ 44 5.4.1 Instruction Register (IR) ............................................................................................................. 44 5.4.2 Data Registers .......................................................................................................................... 46 6 System Control ................................................................................................................... 48 6.1 Functional Description ............................................................................................................... 48 6.1.1 Device Identification .................................................................................................................. 48 6.1.2 Reset Control ............................................................................................................................ 48 3 October 01, 2007 Preliminary LM3S600 Microcontroller |
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