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ORT42G5-1BMN484I Datasheet(PDF) 1 Page - Lattice Semiconductor |
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ORT42G5-1BMN484I Datasheet(HTML) 1 Page - Lattice Semiconductor |
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1 / 119 page  www.latticesemi.com 1 DS1027_07.0 ORCA ® ORT42G5 and ORT82G5 0.6 to 3.7 Gbps XAUI and FC FPSCs July 2008 Data Sheet DS1027 © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Introduction Lattice Semiconductor has developed a family of next generation FPSCs intended for high-speed serial backplane data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the ORT42G5 and ORT82G5 are made up of SERDES transceivers containing four and eight channels respectively. Each channel operates at up to 3.7 Gbps across 26 inches of FR-4 backplane, with a full-duplex synchronous inter- face with built-in Rx Clock and Data Recovery (CDR), and transmitter preemphasis, along with more than 400K usable FPGA system gates. The CDR circuitry available from Lattice’s high-speed I/O portfolio (sysHSI™), has already been proven in numerous applications, to create interfaces for SONET/SDH, Fibre Channel, and Ethernet (GbE, 10 GbE) applications. Designers can also use these devices to drive high-speed data transfer across buses within any generic system. For example, designers can build a bridge for 10 G Ethernet: the high-speed SERDES interfaces can implement a XAUI interface with a configurable back-end interface such as XGMII. The ORT42G5 and ORT82G5 can also be used to provide a full 10 G backplane data connection and, in the case of the ORT82G5, provide both work and protection links between a line card and switch fabric. The ORT42G5 and ORT82G5 provide a clockless high-speed interface for interdevice communication on a board or across a backplane. The built-in clock recovery of the ORT42G5 and ORT82G5 allows for higher system perfor- mance, easier-to-design clock domains in a multiboard system, and fewer signals on the backplane. Network designers will benefit from the backplane transceiver as a network termination device. The device supports embed- ded 8b/10b encoding/decoding and link state machines for 10 G Ethernet, and Fibre Channel. The ORT82G5 is pinout compatible with a sister device, the ORSO82G5, which implements eight channels of SERDES with SONET scrambling and cell processing. The ORT42G5 is pin compatible with the ORSO42G5, which implements four channels of SERDES with SONET scrambling and cell processing. Table 1. ORCA ORT42G5 and ORT82G5 Family – Available FPGA Logic Device PFU Rows PFU Columns Total PFUs FPGA Max. User I/O LUTs EBR Blocks 2 EBR Bits 2 (K) FPGA System Gates (K) 1 ORT42G5 36 36 1296 204 10,368 12 111 333-643 ORT82G5 36 36 1296 372 10,368 12 111 333-643 1. The embedded core, Embedded System Bus, FPGA interface and MPI are not included in the above gate counts. The system gate ranges are derived from the following: Minimum System Gates assumes 100% of the PFUs are used for logic only (No PFU RAM) with 40% EBR usage and two PLLs. Maximum System Gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage and four PLLs. 2. There are two 4K x 36 (144K bits each) RAM blocks in the embedded core which are also accessible by the FPGA logic. |
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