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XP2-17 Datasheet(PDF) 7 Page - Lattice Semiconductor |
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XP2-17 Datasheet(HTML) 7 Page - Lattice Semiconductor |
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7 / 92 page  2-4 Architecture Lattice Semiconductor LatticeXP2 Family Data Sheet Figure 2-3. Slice Diagram Table 2-2. Slice Signal Descriptions Function Type Signal Names Description Input Data signal A0, B0, C0, D0 Inputs to LUT4 Input Data signal A1, B1, C1, D1 Inputs to LUT4 Input Multi-purpose M0 Multipurpose Input Input Multi-purpose M1 Multipurpose Input Input Control signal CE Clock Enable Input Control signal LSR Local Set/Reset Input Control signal CLK System Clock Input Inter-PFU signal FCI Fast Carry-In 1 Input Inter-slice signal FXA Intermediate signal to generate LUT6 and LUT7 Input Inter-slice signal FXB Intermediate signal to generate LUT6 and LUT7 Output Data signals F0, F1 LUT4 output register bypass signals Output Data signals Q0, Q1 Register outputs Output Data signals OFX0 Output of a LUT5 MUX Output Data signals OFX1 Output of a LUT6, LUT7, LUT8 2 MUX depending on the slice Output Inter-PFU signal FCO Slice 2 of each PFU is the fast carry chain output 1 1. See Figure 2-3 for connection details. 2. Requires two PFUs. LUT4 & CARRY* LUT4 & CARRY* SLICE A0 C0 D0 FF* OFX0 F0 Q0 A1 B1 C1 D1 CI CI CO CO CE CLK LSR FF* OFX1 F1 Q1 F/SUM F/SUM D D M1 FCI into Slice/PFU, FCO from Different Slice/PFU FCO from Slice/PFU, FCI into Different Slice/PFU LUT5 Mux M0 From Routing To Routing FXB FXA B0 For Slices 0 and 2, memory control signals are generated from Slice 1 as follows: WCK is CLK WRE is from LSR DI[3:2] for Slice 2 and DI[1:0] for Slice 0 data WAD [A:D] is a 4bit address from slice 1 LUT input * Not in Slice 3 |
Similar Part No. - XP2-17 |
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Similar Description - XP2-17 |
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