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ORSO42G5-1BM484I Datasheet(PDF) 4 Page - Lattice Semiconductor |
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ORSO42G5-1BM484I Datasheet(HTML) 4 Page - Lattice Semiconductor |
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4 / 153 page  Lattice Semiconductor ORCA ORSO42G5 and ORSO82G5 Data Sheet 4 • Optional cell processing blocks included. Cell processing includes cell creation, extraction, idle cell insertion and deletion asynchronous from line rates. Four cell sizes supported: – 77 bytes per cell (75 bytes of data payload) – 81 bytes per cell (79 bytes of data payload) – 85 bytes per cell (83 bytes of data payload) – 93 bytes per cell (91 bytes of data payload) • Automatic cell striping across either pairs of SERDES links or, for the ORSO82G5, all eight SERDES links. • Addition of two 4K X 36 dual-port RAMs accessible by the programmable logic. Programmable Features • High-performance programmable logic: – 0.16 µm 7-level metal technology. – Internal performance of >250 MHz. – Over 400K usable system gates. – Meets multiple I/O interface standards. – 1.5V operation (30% less power than 1.8V operation) translates to greater performance. • Traditional I/O selections: – LVTTL (3.3V) and LVCMOS (2.5V, and 1.8V) I/Os. – Per pin-selectable I/O clamping diodes provide 3.3V PCI compliance. – Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source. – Two slew rates supported (fast and slew-limited). – Fast-capture input latch and input Flip-Flop (FF)/latch for reduced input setup time and zero hold time. – Fast open-drain drive capability. – Capability to register 3-state enable signal. – Off-chip clock drive capability. – Two-input function generator in output path. • New programmable high-speed I/O: – Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I and II), HSTL (Class I, III, IV), ZBT, and DDR. – Double-ended: LVDS, bused-LVDS, and LVPECL. Programmable (on/off), internal parallel termination (100 Ω) is also supported for these I/Os. • New capability to (de)multiplex I/O signals: – New DDR on both input and output. – New 2x and 4x downlink and uplink capability per I/O. • Enhanced twin-block Programmable Function Unit (PFU): – Eight 16-bit Look-Up Tables (LUTs) per PFU. – Nine user registers per PFU, one following each LUT, and organized to allow two nibbles to act indepen- dently, plus one extra for arithmetic operations. – New register control in each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects. – New LUT structure allows flexible combinations of LUT4, LUT5, new LUT6, 4 → 1 MUX, new 8 → 1 MUX, and ripple mode arithmetic functions in the same PFU. – 32 x 4 RAM per PFU, configurable as single-port or dual-port. Create large, fast RAM/ROM blocks (128 x 8 in only eight PFUs) using the Supplemental Logic and Interconnect Cell (SLIC) decoders as bank drivers. – Soft-Wired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU through fast internal routing which reduces routing congestion and improves speed. – Flexible fast access to PFU inputs from routing. – Fast-carry logic and routing to all four adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic func- tions, with the option to register the PFU carry-out. |
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