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OR4E04-2BM680C Datasheet(PDF) 5 Page - Lattice Semiconductor |
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OR4E04-2BM680C Datasheet(HTML) 5 Page - Lattice Semiconductor |
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5 / 152 page  Lattice Semiconductor 5 Data Sheet May, 2006 ORCA Series 4 FPGAs Product Description Architecture Overview The ORCA Series 4 architecture is a new generation of SRAM-based programmable devices from Lattice. It includes enhancements and innovations geared toward today’s high-speed systems on a single chip. Designed with networking applications in mind, the Series 4 fam- ily incorporates system-level features that can further reduce logic requirements and increase system speed. ORCA Series 4 devices contain many new patented enhancements and are offered in a variety of pack- ages, and speed grades. The hierarchical architecture of the logic, clocks, rout- ing, RAM and system level blocks create a seamless merge of FPGA and ASIC designs. Modular hardware and software technologies enable system-on-chip inte- gration with True Plug and Play design implementation. The architecture consists of four basic elements: pro- grammable logic cells (PLCs), programmable input/out- put cells (PIOs), embedded block RAMs (EBRs), and system-level features. A high-level block diagram is shown in Figure 1. These elements are interconnected with a rich routing fabric of both global and local wires. An array of PLCs and its associated resources are sur- rounded by common interface blocks (CIBs) which pro- vide an abundant interface to the adjacent PIOs or system blocks. Routing congestion around these criti- cal blocks is eliminated by the use of the same routing fabric implemented within the programmable logic core. PICS provide the logical interface to the PIOs which provide the boundary interface off and onto the device. Also the interquad routing blocks (hIQ, vIQ) separate the quadrants of the PLC array and provide the global routing and clocking elements. Each PLC contains a PFU, SLIC, local routing resources, and configuration RAM. Most of the FPGA logic is per- formed in the PFU, but decoders, PAL-like functions, and 3-state buffering can be performed in the SLIC. The PIOs provide device inputs and outputs and can be used to register signals and to perform input demul- tiplexing, output multiplexing, uplink and downlink func- tions, and other functions on two output signals. The Series 4 architecture integrates macrocell blocks of memory known as EBR. The blocks run horizontally across the PLC array and provide flexible memory functionality. Large blocks of 512x18 quad-port RAM compliment the existing distributed PFU memory. The RAM blocks can be used to implement RAM, ROM, FIFO, multiplier, and CAM, typically without the use of PFUs for implementation. System-level functions such as a microprocessor inter- face, PLLs, embedded system bus elements (located in the corners of the array), the routing resources, and configuration RAM are also integrated elements of the architecture. For Series 4 FPSCs, all PIO buffers and logic are replaced by the embedded logic core on the side of the device. The four PLLs on the right side of the device (two in the upper right corner and two in the lower right corner) are removed and the embedded system bus extends into the FPSC section. |
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