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OR4E04-2BM416C Datasheet(PDF) 10 Page - Lattice Semiconductor |
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OR4E04-2BM416C Datasheet(HTML) 10 Page - Lattice Semiconductor |
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10 / 152 page  10 Lattice Semiconductor Data Sheet May, 2006 ORCA Series 4 FPGAs Programmable Logic Cells (continued) Look-Up Table Operating Modes The operating mode affects the functionality of the PFU input and output ports and internal PFU routing. For exam- ple, in some operating modes, the DIN[7:0] inputs are direct data inputs to the PFU latches/FFs. In memory mode, the same DIN[7:0] inputs are used as a 4-bit write data input bus and a 4-bit write address input bus into LUT memory. Table 2 lists the basic operating modes of the LUT. Figure 4—Figure 7 show block diagrams of the LUT operating modes. The accompanying descriptions demonstrate each mode’s use for generating logic. Table 2. Look-Up Table Operating Modes PFU Control Inputs Each PFU has eight routable control inputs and an active-low, asynchronous global set/reset (GSRN) signal that affects all latches and FFs in the device. The eight control inputs are CLK[1:0], LSR[1:0], CE[1:0], and SEL[1:0], and their functionality for each logic mode of the PFU is shown in Table 3. The clock signal to the PFU is CLK, CE stands for clock enable, which is its primary function. LSR is the local set/reset signal that can be configured as synchronous or asynchronous. The selection of set or reset is made for each latch/FF and is not a function of the signal itself. SEL is used to dynamically select between direct PFU input and LUT output data as the input to the latches/FFs. All of the control signals can be disabled and/or inverted via the configuration logic. A disabled clock enable indicates that the clock is always enabled. A disabled LSR indicates that the latch/FF never sets/resets (except from GSRN). A disabled SEL input indicates that DIN[7:0] PFU inputs are routed to the latches/FFs. Table 3. Control Input Functionality Mode Function Logic 4-, 5-, and 6-input LUTs; softwired LUTs; latches/FFs with direct input or LUT input; CIN as direct input to ninth FF or as pass through to COUT. Half Logic/ Half Ripple Upper four LUTs and latches/FFs in logic mode; lower four LUTs and latches/FFs in ripple mode; CIN and ninth FF for logic or ripple functions. Ripple All LUTs combined to perform ripple-through data functions. Eight LUT registers available for direct-in use or to register ripple output. Ninth FF dedicated to ripple out, if used. The submodes of ripple mode are adder/subtractor, counter, multiplier, and comparator. Memory All LUTs and latches/FFs used to create a 32x4 synchronous dual-port RAM. Can be used as single-port or as ROM. Mode CLK [1:0] LSR [1:0] CE [1:0] SEL [1:0] Logic CLK to all latches/ FFs LSR to all latches/FFs, enabled per nibble and for ninth FF CE to all latches/FFs, selectable per nibble and for ninth FF Select between LUT input and direct input for eight latches/FFs Half Logic/ Half Ripple CLK to all latches/ FFs LSR to all latches/FF, enabled per nibble and for ninth FF CE to all latches/FFs, selectable per nibble and for ninth FF Select between LUT input and direct input for eight latches/FFs Ripple CLK to all latches/ FFs LSR to all latches/FFs, enabled per nibble and for ninth FF CE to all latches/FFs, selectable per nibble and for ninth FF Select between LUT input and direct input for eight latches/FFs Memory (RAM) CLK to RAM LSR0 Port enable 2 CE1 RAM write enable CE0 Port enable 1 Not used Memory (ROM) Optional for synchronous outputs Not used Not used Not used |
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