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ORLI10G-1BMN680I Datasheet(PDF) 6 Page - Lattice Semiconductor |
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ORLI10G-1BMN680I Datasheet(HTML) 6 Page - Lattice Semiconductor |
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6 / 80 page  Lattice Semiconductor ORCA ORLI10G Data Sheet 6 timing requirement information through logical preferences only; thus, the designer is not required to have physical knowledge of the implementation. Following design entry, the development system's map, place, and route tools translate the netlist into a routed FPGA. A floor planner is available for layout feedback and control. A static timing analysis tool is provided to deter- mine design speed, and a back-annotated netlist can be created to allow simulation and timing. Timing and simulation output files from ispLEVER are also compatible with many third-party analysis tools. A bit stream generator is then used to generate the configuration data which is loaded into the FPGAs internal configu- ration RAM, embedded block RAM, and/or FPSC memory. When using the bit stream generator, the user selects options that affect the functionality of the FPGA. Combined with the front-end tools, ispLEVER produces configuration data that implements the various logic and routing options discussed in this data sheet. FPSC Design Kit Development is facilitated by an FPSC design kit which, together with ispLEVER software and third-party synthesis and simulation engines, provides all software and documentation required to design and verify an FPSC implemen- tation. Included in the kit are the FPSC configuration manager, Synopsys Smart Model ®, and/or compiled Verilog ® simulation model, HSPICE ® and/or IBIS models for I/O buffers, and complete online documentation. The kit's soft- ware couples with ispLEVER software, providing a seamless FPSC design environment. More information can be obtained by visiting the Lattice website at www.latticesemi.com or contacting a local sales office. ORLI10G FPGA Logic Overview The following sections provide a brief overview of the main architectural features of the ORLI10G FPGA logic. For more detailed information, please refer to the ORCA Series 4 FPGA Data Sheet which can be found under the “Products” folder on the Lattice Semiconductor main Web site: www.latticesemi.com. The ORCA Series 4 FPGA Data Sheet provides detailed information required for designing with the ORLI10G device. Topics covered in the ORCA Series 4 Data Sheet include: • FPGA Logic Architecture • FPGA Routing Resources • FPGA Clock Routing Resources • FPGA Programmable Input/Output Cells (PICs) • FPGA Embedded Block RAM (EBR) • Microprocessor Interface (MPI) • Phase-Locked Loops (PLLs) • Electrical Characteristics • FPGA Timing Characteristics • Power-up • Configuration ORCA Series 4 FPGA Logic Overview The ORCA Series 4 architecture is a new generation of SRAM-based programmable devices from Lattice. It includes enhancements and innovations geared toward today's high-speed systems on a single chip. Designed with networking applications in mind, the Series 4 family incorporates system-level features that can further reduce logic requirements and increase system speed. ORCA Series 4 devices contain many new patented enhance- ments and are offered in a variety of packages and speed grades. |
Similar Part No. - ORLI10G-1BMN680I |
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Similar Description - ORLI10G-1BMN680I |
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