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LAMXO256LUTSC-3FTN324E Datasheet(PDF) 6 Page - Lattice Semiconductor |
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LAMXO256LUTSC-3FTN324E Datasheet(HTML) 6 Page - Lattice Semiconductor |
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6 / 77 page  2-3 Architecture Lattice Semiconductor LA-MachXO Automotive Family Data Sheet Figure 2-3. Top View of the LA-MachXO256 Device PFU Blocks The core of the LA-MachXO devices consists of PFU and PFF blocks. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM, and Distributed ROM functions. PFF blocks can be programmed to perform Logic, Arithmetic, and Distributed ROM functions. Except where necessary, the remainder of this data sheet will use the term PFU to refer to both PFU and PFF blocks. Each PFU block consists of four interconnected Slices, numbered 0-3 as shown in Figure 2-4. There are 53 inputs and 25 outputs associated with each PFU block. Figure 2-4. PFU Diagram Slice Each Slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7, and LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select, and wider RAM/ROM functions. Figure 2-5 shows an overview of the internal logic of the Slice. The registers in the Slice can be configured for positive/negative and edge/level clocks. JTAG Port Programmable Function Units with RAM (PFUs) Programmable Function Units without RAM (PFFs) PIOs Arranged into sysIO Banks Slice 0 LUT4 & CARRY LUT4 & CARRY FF/ Latch FCIN FCO D FF/ Latch D Slice 1 LUT4 & CARRY LUT4 & CARRY Slice 2 LUT4 & CARRY LUT4 & CARRY From Routing To Routing Slice 3 LUT4 & CARRY LUT4 & CARRY FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D |
Similar Part No. - LAMXO256LUTSC-3FTN324E |
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