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OR4E02-1BM680C Datasheet(PDF) 9 Page - Lattice Semiconductor |
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OR4E02-1BM680C Datasheet(HTML) 9 Page - Lattice Semiconductor |
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9 / 152 page  Lattice Semiconductor 9 Data Sheet May, 2006 ORCA Series 4 FPGAs Programmable Logic Cells (continued) 5-9714(F) Note: All multiplexers without select inputs are configuration selector multiplexers. Figure 3. Simplified PFU Diagram K3_0MUX K7_0MUX D0 D1 SD SP CK LSR REG7 RESET SET Q7 F7 0 DIN7 DIN7MUX D0 D1 SD SP CK LSR REG6 RESET SET Q6 F6 0 DIN6 DIN6MUX D0 D1 SD SP CK LSR REG5 RESET SET Q5 F5 0 DIN5 DIN5MUX D0 D1 SD SP CK LSR REG4 RESET SET Q4 F4 0 DIN4 DIN4MUX LUT647 0 A B C D A B C D A B C D A B C D FSDMUX K7_2MUX K6_0MUX K6_2MUX AMUX H7H6MUX K7 K6 K5 K4 FSCMUX H5H4MUX LUT6MUX F5D K7_0 K7_1 K7_2 K7_3 K6_0 K6_1 K6_2 K6_3 K5_0 K5_1 K5_2 K5_3 K4_0 K4_1 K4_2 F5C K4_3 D0 D1 SD SP CK LSR REG3 RESET SET Q3 F3 0 DIN3 DIN3MUX D0 D1 SD SP CK LSR REG2 RESET SET Q2 F2 0 DIN2 DIN2MUX D0 D1 SD SP CK LSR REG1 RESET SET Q1 F1 0 DIN1 DIN1MUX D0 D1 SD SP CK LSR REG0 RESET SET DEL0 DEL1 DEL2 Q0 F0 0 DIN0 DIN0MUX LUT603 0 A B C D A B C D A B C D A B C D FSBMUX K3_2MUX K2_0MUX K2_2MUX BMUX H3H2MUX K3 K2 K1 K0 F5AMUX H1H0MUX LUT6MUX F5B K3_0 K3_1 K3_2 K3_3 K2_0 K2_1 K2_2 K2_3 K1_0 K1_1 K1_2 K1_3 K0_0 K0_1 K0_2 F5A K0_3 0 CLK1 CLK1MUX 0 SEL1 SEL1MUX 1 CE1 CE1MUX CE47MUX 0 LSR1 LSR1MUX LSR47MUX 0 CIN 1 0 0 CLK0 CLK0MUX 0 SEL0 SEL0MUX 1 CE0 CE0MUX CEBMUX 0 LSR0 LSR0MUX CE03MUX 1 0 LSRBMUX LSR03MUX 1 0 D0 SP CK LSR REG8 RESET SET RECCOUT COUT SR1MODEATTR SR1MODE CE1_OVER_LSR1 LSR1_OVER_CE1 RSYNC1 SR0MODEATTR SR0MODE CE0_OVER_LSR0 LSR0_OVER_CE0 ASYNC0 REGMODE_TOP FF LATCH REG 4 THROUGH 7 THIS IS ALWAYS A FLIPFLOP REGMODE_BOT FF LATCH REG 0 THROUGH 3 LOGIC MLOGIC RIPPLE RAM ROM ENABLED DISABLED GSR PFU MODES CINMUX 0 0 DEL3 DEL0 DEL1 DEL2 DEL3 DEL0 DEL1 DEL2 DEL3 DEL0 DEL1 DEL2 DEL3 DEL0 DEL1 DEL2 DEL3 DEL0 DEL1 DEL2 DEL3 DEL0 DEL1 DEL2 DEL3 DEL0 DEL1 DEL2 DEL3 DEL0 DEL1 DEL2 DEL3 |
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