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ORT8850 Datasheet(PDF) 71 Page - Lattice Semiconductor

Part # ORT8850
Description  Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

ORT8850 Datasheet(HTML) 71 Page - Lattice Semiconductor

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Lattice Semiconductor
ORCA ORT8850 Data Sheet
71
HSI Electrical and Timing Characteristics
Table 22. Maximum Power Dissipation
Table 23. Recommended Operating Conditions
Table 24. Receiver Specifications
Parameter
Conditions
Min.
Typ.
Max.
Units
Power Dissipation
SERDES, scrambler/descrambler, framer,
FIFO alignment, pointer mover, and I/O
(per channel), 622 Mbtis/s
125
mW
1. With all channels operating, 1.575 V and 3.6 V supplies, 85ºC.
Parameter
Conditions
Min.
Typ.
Max.
Units
VDD15 Supply Voltage
1.425
1.575
V
Junction Temperature
TJ
–40
125
°C
Parameter
Conditions
Min.
Typ.
Max.
Units
Input Data
Stream of Nontransitions
1
72
bits
Phase Change, Input Signal
Over a 200 ns time interval
2
100
ps
Eye Opening
3
0.4
UIp-p
Jitter Tolerance @ 622 Mbits/s, Worst Case
300 MV diff eye
4
0.6
UIp-p
Jitter Tolerance @ 155 Mbits/s, Worst Case
250 MV diff eye
5
0.85
UIp-p
1. This sequence should not occur more than once per minute.
2. Translates to a frequency change of 500 ppm.
3. A unit interval for 622.08 Mbits/s data is 1.6075 ns.
4. With STS-12 data pattern, all channels operating, FPGA logic active, REFCLK jitter of 30 ps., TA=0°C to 85°C, 1.425 V to 1.575 V supply. Jit-
ter measured with a Wavecrest SIA-3000.
5. With STS-3 data pattern, all channels operating, FPGA logic active, REFCLK jitter of 30 ps., TA=0°C to 85°C, 1.425 V to 1.575 V supply. Jit-
ter measured with a Wavecrest SIA-3000.


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