Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

ORT8850 Datasheet(PDF) 48 Page - Lattice Semiconductor

Part # ORT8850
Description  Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
Download  105 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

ORT8850 Datasheet(HTML) 48 Page - Lattice Semiconductor

Back Button ORT8850 Datasheet HTML 44Page - Lattice Semiconductor ORT8850 Datasheet HTML 45Page - Lattice Semiconductor ORT8850 Datasheet HTML 46Page - Lattice Semiconductor ORT8850 Datasheet HTML 47Page - Lattice Semiconductor ORT8850 Datasheet HTML 48Page - Lattice Semiconductor ORT8850 Datasheet HTML 49Page - Lattice Semiconductor ORT8850 Datasheet HTML 50Page - Lattice Semiconductor ORT8850 Datasheet HTML 51Page - Lattice Semiconductor ORT8850 Datasheet HTML 52Page - Lattice Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 48 / 105 page
background image
Lattice Semiconductor
ORCA ORT8850 Data Sheet
48
SYS_FP
I
System frame pulse generated inside the FPGA logic. This is a sin-
gle clock pulse of FPGA_SYSCLK every 9720 clock cycles. For a
77.76 MHz reference clock the system frame pulse is at the SONET
standard of 8 KHz. All the eight Transmit channels' first A1 byte
should be aligned to the SYS_FP. Internally SYS_FP is used when
Far end loopback (line side loopback) needs to be performed. This
loopback can only be performed when Pointer Mover is not
bypassed.
LINE_FP
I
User-provided frame pulse used by only the Pointer Mover block in
the receive direction. The Pointer Mover moves the data to align it
with the LINE_FP. If the Pointer Mover is bypassed, LINE_FP is not
used.
TOH_CLK
I
Clock driven from the FPGA to clock the TOH processor. This clock
can be in the range from 25MHz to 77.76MHz. If not using the TOH
communication channel this signal can be connected to GND.
Signals to TX Logic Blocks
DINxx[7:0]
I
Byte wide data for channel xx. This data is ultimately preset on the
serial LVDS pin TXDxx_W_[P:N] (work) and TXDxx_P_[P:N] (pro-
tect).
DINxx_PAR
I
Parity input for byte wide data DINxx. Odd or even parity selection
is controlled by a bit in the control register at 0x3000C.
Signals from RX Logic Blocks
DOUTxx[7:0]
O
Byte wide data for channel AA
DOUTxx_PAR
O
Parity output for byte wide data DOUTxx[7:0]. Odd/Even is con-
trolled by control register at 0x3000C.
DOUTxx_FP
O
Frame pulse output from the SONET framer. A single clock pulse to
indicate the start of the SONET frame. If bypassing the pointer
mover/interpreter this pulse will line up directly with the first A1 on
DOUTxx[7:0]. If using the pointer interpreter/mover DOUTxx_FP
will fall several clock cycles before the A1 on DOUTxx[7:0] due to
the latency from the pointer mover.
DOUTxx_SPE
O
When '1' indicates SPE bytes are on the DOUTxx[7:0] lines. Only
available when using the pointer interpreter/mover
DOUTxx_C1J1
O
When '1' indicates the C1J1 bytes are on the DOUTxx[7:0] lines.
Only available when using the pointer interpreter/mover.
DOUTxx_EN
O
Indicates the state of register setting for DOUTxx_EN.
CDR_CLK_xx
O
Recovered clock from the Channel xx SERDES. If not using the
alignment FIFO all of the parallel data from Channel xx will be
clocked from this clock.
Signals to TOH Logic Blocks (Note: These signals are active only in the serial TOH insertion mode)
TX_TOH_CK_EN
I
Active-hi TOH_CLK enable. If using serial TOH insertion this enable
must be active.
TOH_INxx
I
Serial TOH insertion port for channel xx.
Signals from TOH Logic Blocks (Note: These signals are active only in the serial TOH insertion mode)
RX_TOH_CK_EN
O
When '1' indicates a control register bit has been set to enable the
TOH clock and frame pulse.
RX_TOH_FP
O
Single clock frame pulse to indicate the serial link frame pulse.
TOH_CK_FP_EN
O
When '1' indicates the TOH serial link clock is enabled.
TOH_OUTxx
O
TOH serial link output from Channel xx
Table 15. FPGA/Embedded Core Interface Signals (Continued)
ORT8850 FPGA/Embedded Core Interface Signals - SONET Blocks
FPGA/Embedded Core
Interface Signal Name
xx=[AA,…,BD]
Input (I) to or Output (O)
from Core
Signal Description


Similar Part No. - ORT8850

ManufacturerPart #DatasheetDescription
logo
Agere Systems
ORT8850 AGERE-ORT8850 Datasheet
2Mb / 112P
   Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
ORT8850H AGERE-ORT8850H Datasheet
2Mb / 112P
   Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
ORT8850L AGERE-ORT8850L Datasheet
2Mb / 112P
   Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
More results

Similar Description - ORT8850

ManufacturerPart #DatasheetDescription
logo
Agere Systems
ORT8850 AGERE-ORT8850 Datasheet
2Mb / 112P
   Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
ORT4622 AGERE-ORT4622 Datasheet
1Mb / 90P
   Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver
OR3TP12 AGERE-OR3TP12 Datasheet
2Mb / 128P
   Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
OR3LP26B AGERE-OR3LP26B Datasheet
5Mb / 184P
   Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
DNC3X3125 AGERE-DNC3X3125 Datasheet
460Kb / 32P
   DNC3X3125 10/100 Mbits/s Ethernet Transceiver Macrocell
DNC3X3625 AGERE-DNC3X3625 Datasheet
464Kb / 32P
   Hex 10/100 Mbits/s Ethernet Transceiver Macrocell
DNC3X3825 AGERE-DNC3X3825 Datasheet
465Kb / 32P
   Octal 10/100 Mbits/s Ethernet Transceiver Macrocell
DNC3X3425 AGERE-DNC3X3425 Datasheet
757Kb / 32P
   DNC3X3425 Quad 10/100 Mbits/s Ethernet Transceiver Macrocell
logo
SMSC Corporation
EVB-USB2514Q36-BAS SMSC-EVB-USB2514Q36-BAS Datasheet
269Kb / 6P
   Hi-Speed (480 Mbits/s), Full-Speed (12 Mbits/s), and Low-Speed (1.5 Mbits/s) compatible
EVB-USB2517 SMSC-EVB-USB2517 Datasheet
499Kb / 6P
   Hi-Speed (480 Mbits/s), Full-Speed (12 Mbits/s), and Low-Speed (1.5 Mbits/s) compatible
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com