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ORT8850 Datasheet(PDF) 48 Page - Lattice Semiconductor |
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ORT8850 Datasheet(HTML) 48 Page - Lattice Semiconductor |
48 / 105 page Lattice Semiconductor ORCA ORT8850 Data Sheet 48 SYS_FP I System frame pulse generated inside the FPGA logic. This is a sin- gle clock pulse of FPGA_SYSCLK every 9720 clock cycles. For a 77.76 MHz reference clock the system frame pulse is at the SONET standard of 8 KHz. All the eight Transmit channels' first A1 byte should be aligned to the SYS_FP. Internally SYS_FP is used when Far end loopback (line side loopback) needs to be performed. This loopback can only be performed when Pointer Mover is not bypassed. LINE_FP I User-provided frame pulse used by only the Pointer Mover block in the receive direction. The Pointer Mover moves the data to align it with the LINE_FP. If the Pointer Mover is bypassed, LINE_FP is not used. TOH_CLK I Clock driven from the FPGA to clock the TOH processor. This clock can be in the range from 25MHz to 77.76MHz. If not using the TOH communication channel this signal can be connected to GND. Signals to TX Logic Blocks DINxx[7:0] I Byte wide data for channel xx. This data is ultimately preset on the serial LVDS pin TXDxx_W_[P:N] (work) and TXDxx_P_[P:N] (pro- tect). DINxx_PAR I Parity input for byte wide data DINxx. Odd or even parity selection is controlled by a bit in the control register at 0x3000C. Signals from RX Logic Blocks DOUTxx[7:0] O Byte wide data for channel AA DOUTxx_PAR O Parity output for byte wide data DOUTxx[7:0]. Odd/Even is con- trolled by control register at 0x3000C. DOUTxx_FP O Frame pulse output from the SONET framer. A single clock pulse to indicate the start of the SONET frame. If bypassing the pointer mover/interpreter this pulse will line up directly with the first A1 on DOUTxx[7:0]. If using the pointer interpreter/mover DOUTxx_FP will fall several clock cycles before the A1 on DOUTxx[7:0] due to the latency from the pointer mover. DOUTxx_SPE O When '1' indicates SPE bytes are on the DOUTxx[7:0] lines. Only available when using the pointer interpreter/mover DOUTxx_C1J1 O When '1' indicates the C1J1 bytes are on the DOUTxx[7:0] lines. Only available when using the pointer interpreter/mover. DOUTxx_EN O Indicates the state of register setting for DOUTxx_EN. CDR_CLK_xx O Recovered clock from the Channel xx SERDES. If not using the alignment FIFO all of the parallel data from Channel xx will be clocked from this clock. Signals to TOH Logic Blocks (Note: These signals are active only in the serial TOH insertion mode) TX_TOH_CK_EN I Active-hi TOH_CLK enable. If using serial TOH insertion this enable must be active. TOH_INxx I Serial TOH insertion port for channel xx. Signals from TOH Logic Blocks (Note: These signals are active only in the serial TOH insertion mode) RX_TOH_CK_EN O When '1' indicates a control register bit has been set to enable the TOH clock and frame pulse. RX_TOH_FP O Single clock frame pulse to indicate the serial link frame pulse. TOH_CK_FP_EN O When '1' indicates the TOH serial link clock is enabled. TOH_OUTxx O TOH serial link output from Channel xx Table 15. FPGA/Embedded Core Interface Signals (Continued) ORT8850 FPGA/Embedded Core Interface Signals - SONET Blocks FPGA/Embedded Core Interface Signal Name xx=[AA,…,BD] Input (I) to or Output (O) from Core Signal Description |
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