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ORT42G5 Datasheet(PDF) 55 Page - Lattice Semiconductor |
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ORT42G5 Datasheet(HTML) 55 Page - Lattice Semiconductor |
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55 / 119 page  Lattice Semiconductor ORCA ORT42G5 and ORT82G5 Data Sheet 55 Parallel Loopback at MUX/DEMUX Boundary, Excluding SERDES This is a low-frequency test mode used to test the MUX/DEMUX logic block. As with the mode described in the pre- vious section, the loopback path is at the interface between the SERDES blocks and the MUX and DEMUX blocks and uses the parallel 10-bit buses at these interfaces (see Figure 33). However, the loopback connection is made such that the output signals from the TX MUX block are used as the input signals to the RX SERDES block. In this loopback mode the MRWDxx[39:0], TWDxx[31:0], TCOMMAxx[3:0] and TBIT9xx[3:0] signal lines function normally and the high-speed serial input and output buffers are not used. Use of this mode also requires configuration of the FPGA logic to connect the MRWDxx[39:0], TWDxx[31:0], TCOMMAxx[3:0] and TBIT9xx[3:0] signal lines to exter- nal pins. The basic loopback path is shown in Figure 33. Figure 33. Parallel Loopback at MUX/DEMUX Boundary, Excluding SERDES This test mode is enabled by setting the pin PLOOP_TEST_ENN to 0. PASB_TESTCLK must be running in this mode at 4x frequency of RSYS_CLK[A2, B2] or TSYS_CLK_[AC, AD, BC, BD] for the ORT42G5 and RSYS_CLK[A1,A2,B1,B2] or TSYS_CLK_[AA, AB... BD] for the ORT82G5. SERDES Characterization Test Mode (ORT82G5 Only) The SERDES characterization mode is a test mode that allows for direct control and observation of the transmit and receive SERDES interfaces at chip ports. With these modes the SERDES logic and I/O can be tested one channel at a time in either the receive or transmit modes. The SERDES characterization mode is available for only one quad (quad B) of the ORT82G5. The characterization test mode is configured by setting bits in the control registers via the system bus. There are four bits that set up the test mode. The transmit characterization test mode is entered when SCHAR_ENA=1 and SCHAR_TXSEL=1. Entering this mode will cause chip port inputs to directly control the SERDES low-speed trans- mit ports of one of the channels as shown in Table 23. Table 23. SERDES Transmit Characterization Mode The x in the table will be a single channel in SERDES quad B, selected by the SCHAR_CHAN control bits. The decoding of SCHAR_CHAN is shown in Table 24. Chip Port SERDES Input PSCHAR_CKIO0 TBCBx PSCHAR_LDIO[9:0] LDINBx[9:0] DEMUX MUX Embedded Core FPGA Logic 40 MRWDxx[39:0] 32 4 4 Receive Transmit TWDxx[31:0] TCOMMAxx[3:0] TBIT9xx[3:0] Data Checking Data Generation n m { Parallel Loopback Connection Test Equipment |
Similar Part No. - ORT42G5 |
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Similar Description - ORT42G5 |
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